Unité

Laboratoire d'architecture des processeurs

Laboratoire

Résumé

Le Laboratoire d'architecture des processeurs de l'EPFL met l'accent sur l'interaction entre l'architecture informatique, la technologie du compilateur et la mise en œuvre du matériel pour obtenir d'excellentes performances dans les systèmes informatiques. Dirigé par le directeur Paolo Ienne, le laboratoire vise à comprendre et exploiter les synergies dans ces domaines, en transmettant les connaissances aux étudiants à travers des projets et des cours.

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Résumé

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Personnes associées (4)

Canberk Sönmez

Ayatallah Ahmed Gamal Kamal Elakhras

Expertise Dataflow ArchitectureHigh-Level Synthesis Ayatallah is a Ph.D. student in the Processor Architecture Laboratory, advised by Professor Paolo Ienne. Between October 2023 and March 2024, she did an internship at AMD in the Research and Advanced Development team, under the supervision of Dr. Kristof Denolf. She received a B.Sc. degree in Computer Engineering from the American University in Cairo, Egypt in 2020 and started her Ph.D. in the same year.Her research interests include dataflow architecture,

Paolo Ienne

Paolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.

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