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Séance de cours

Synchronisation primitives

Dans cours

CS-206: Parallelism and concurrency

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Description

Cette séance de cours couvre la conception de primitives de synchronisation et de structures de données concurrentes en utilisant des instructions atomiques telles que comparer et définir, incrémenter et obtenir, et récupérer et ajouter. Il souligne l'importance du support matériel pour la mise en œuvre de ces structures et l'attention particulière nécessaire pour assurer la sécurité du fil.

Enseignant·e·s (3)

Viktor Kuncak

Viktor Kunčak joined EPFL in 2007, after receiving a PhD degree from MIT. Since then has been leading the Laboratory for Automated Reasoning and Analysis and supervised at least 12 completed PhD theses. His works on languages, algorithms and systems for verification and automated reasoning. He served as an initiator and one of the coordinators of a European network (COST action) in the area of automated reasoning, verification, and synthesis. In 2012 he received a 5-year single-investigator European Research Council (ERC) grant of 1.5M EUR. His invited talks include those at Lambda Days, Scala Days, NFM, LOPSTR, SYNT, ICALP, CSL, RV, VMCAI, and SMT. A paper on test generation he co-authored received an ACM SIGSOFT distinguished paper award at ICSE. A PLDI paper he co-authored was published in the Communications of the ACM as a Research Highlight article. His Google Scholar profile reports an over-approximate H-index of 38. He was an associate editor of ACM Transactions on Programming Languages and Systems (TOPLAS) and served as a co-chair of conferences on Computer-Aided Verification (CAV), Formal Methods in Computer Aided Design (FMCAD), Workshop on Synthesis (SYNT), and Verification, Model Checking, and Abstract Interpretation (VMCAI). At EPFL he teaches courses on functional and parallel programming, compilers, and verification. He has co-taught the MOOC "Parallel Programming" that was visited by over 100'000 learners and completed by thousands of students from all over the world.

Sanidhya Kashyap

Sanidhya Kashyap is a systems researcher and an assistant professor at the EPFL School of Computer and Communication Sciences (IC). His research focuses on designing systems software that are performant and robust for heterogeneous hardware. He is broadly interested in the area of systems with a particular focus on operating systems, databases, concurrency, scheduling, networks, data analytics, and software testing (fuzzing).

Martin Odersky

Martin Odersky heads the programming research group at EPFL. His research interests cover fundamental as well as applied aspects of programming languages. They include semantics, type systems, programming language design, and compiler construction. The main focus if his work lies in the integration of object-oriented and functional programming. His research thesis is that the two paradigms are just two sides of the same coin and should be unified as much as possible. To prove this he has experimented a number of language designs, from Pizza to GJ to Functional Nets. He has also influenced the development of Java as a co-designer of Java generics and as the original author of the current javac reference compiler. His current work concentrates on the Scala programming language, which unifies FP and OOP, while staying completely interoperable with Java and .NET. Martin Odersky got his doctorate from ETHZ, in 1989. He held research positions at the IBM T.J. Watson Research Center from 1989 and at Yale University from 1991. He was then a professor at the University of Karlsruhe from 1993 and at the University of South Australia from 1997. He joined EPFL as full professor in 1999. He is associate editor of the Journal of Functional Programming and member of IFIP WG 2.8. He was conference chair for ICFP 2000, and program chair for ECOOP 2004 as well as ETAPS/CC 2007.

Source officielle

Concepts associés (17)

Non-blocking algorithm

In computer science, an algorithm is called non-blocking if failure or suspension of any thread cannot cause failure or suspension of another thread; for some operations, these algorithms provide a useful alternative to traditional blocking implementations. A non-blocking algorithm is lock-free if there is guaranteed system-wide progress, and wait-free if there is also guaranteed per-thread progress. "Non-blocking" was used as a synonym for "lock-free" in the literature until the introduction of obstruction-freedom in 2003.

Synchronisation (multitâches)

En programmation concurrente, la synchronisation se réfère à deux concepts distincts mais liés : la synchronisation de processus et la synchronisation de données. La synchronisation de processus est un mécanisme qui vise à bloquer l'exécution de certains processus à des points précis de leur flux d'exécution, de manière que tous les processus se rejoignent à des étapes relais données, tel que prévu par le programmeur. La synchronisation de données, elle, est un mécanisme qui vise à conserver la cohérence des données telles que vues par différents processus, dans un environnement multitâche.

Instruction set architecture

In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation. In general, an ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.

Linearizability

In concurrent programming, an operation (or set of operations) is linearizable if it consists of an ordered list of invocation and response events, that may be extended by adding response events such that: The extended list can be re-expressed as a sequential history (is serializable). That sequential history is a subset of the original unextended list. Informally, this means that the unmodified list of events is linearizable if and only if its invocations were serializable, but some of the responses of the serial schedule have yet to return.

Jeu d'instructions x86

Le jeu d'instructions du x86 a subi de nombreux changements au cours du temps. La plupart d'entre eux ne sont que des ajouts au jeu d'instructions initial afin d'apporter de nouvelles fonctionnalités. Ceci est le jeu d'instructions complet pour les processeurs 8086-8088 et la plupart, si ce n'est toutes ces instructions sont accessibles en mode 32 bits. Elles opèrent alors sur les registres et valeurs (eax, ebx, etc.) en lieu et place de leur contrepartie en (ax, bx, etc.).

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Séances de cours associées (37)

Opérations atomiques : notions de base et applications

Couvre les bases des opérations atomiques dans la proximité et le parallélisme, y compris les opérations fournies par le matériel et les algorithmes synchronisés.

L'écluse de l'écrivain

Couvre le concept de verrouillage de Readers Writer et sa synchronisation entre les lecteurs et les écrivains en utilisant des variables atomiques.

Moniteurs : Synchronisation et coopération

Explore les moniteurs comme une construction de synchronisation fournissant l'exclusion mutuelle et la coopération entre les threads, avec des exemples comme le tampon d'un seul endroit.

Concurrence: Deadlock

Couvre le concept d'impasse dans la programmation simultanée et fournit des solutions pour les prévenir.

Exécution atomique: Synchronisation dans les threads

Couvre l'exécution atomique dans les threads, les conditions de course, les variables partagées et les blocs synchronisés.

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Concepts associés (17)

Non-blocking algorithm

Synchronisation (multitâches)

Instruction set architecture

Linearizability

Jeu d'instructions x86

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