Mediaspace scheduled maintenance: Aug 25, 2026 07:00 - 12:00 AM. During this time, videos will be temporarily unavailable. Check status updates.

Home

Person

Gabriel Falcao Paiva Fernandes

This person has left EPFL

About
Privacy
Disclaimer

Graph Chatbot

Related publications (6)

Please note that this is not a complete list of this person’s publications. It includes only semantically relevant works. For a full list, please refer to Infoscience.

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Related publications (6)

Please note that this is not a complete list of this person’s publications. It includes only semantically relevant works. For a full list, please refer to Infoscience.

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes, Madhura Purnaprajna

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

Distributed Learning of CNNs on Heterogeneous CPU/GPU Architectures

José Pedro Rebelo Ferreira Marques, Gabriel Falcao Paiva Fernandes, Alexandre Luisier

The convolutional neural networks (CNNs) have proven to be powerful classification tools in tasks that range from check reading to medical diagnosis, reaching close to human perception, and in some cases surpassing it. However, the problems to solve are be ...

TAYLOR & FRANCIS INC2018

Exploiting Compute Caches for Memory Bound Vector Operations

Paolo Ienne, Gabriel Falcao Paiva Fernandes

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and red ...

IEEE2018