Publications by Giovanni De Micheli

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Environmental energy is becoming a feasible alternative to traditional energy sources for ultra low-power devices such as sensor nodes and smart watches. Moreover, the increas- ing need for exibility and recon gurability of such devices makes its energy ma ...

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

Factored form is a powerful multi-level representa- tion of a Boolean function that readily translates into an imple- mentation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number ...

We present the very first worldwide ever-reported electrochemical biosensor based on a memristive effect and DNA aptamers. This novel device is developed to propose a completely new approach in cancer diagnostics. In this study, an affinity-based technique ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devi ...

Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer from excessive comp ...

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

In this article, we explore adaptive global and local segmentation techniques for a lab-on-chip nutrition monitoring system (NutriChip). The experimental setup consists of Caco-2 intestinal cells that can be artificially stimulated to trigger an immune res ...

Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their uniq ...

The direct electrochemical behaviour of bilirubin in the physio-pathological concentration range and at physio- logical pH was investigated by cyclic voltammetry. Nanostructured electrodes with a thin film of multi-walled carbon nanotubes exhibited a highe ...

Several challenges should be resolved for three dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3 ...

Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on th ...

In-memory computing devices, such as resistive RAMs, natively implement material implication or a variant of the majority-of-three operation called RM3. This operation generalizes material implication and has been used as target operation in sev ...

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. ...

Nanostructured materials have attracted considerable interest over the last few decades to enhance sensing capabilities thanks to their unique properties and large surface area. In particular, noble metal nanostructures offer several advantages including h ...

In this paper, we present a heterogeneous integration of ReRAMs with standard CMOS technology by post-processing the Back-End-of-the-Line (BEOL) of fully finished CMOS chips. ...

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

Manipulating logic functions via majority operators recently drew the attention of researchers in computer science. For example, circuit optimization based on majority operators enables superior results as compared to traditional logic systems. Also, the B ...

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

The design of 3-dimensional integrated circuits requires new specialized tools, methods and flows. Whereas some tools are on the market and some design flows for standard ICs are extended to handle die stacking and through-silicon vias, much R&D has still ...

Giovanni De Micheli

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An Opportunistic Reconfiguration Strategy for Environmentally Powered Devices

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Improving Standard-Cell Design Flow using Factored Form Optimization

Label-Free Ultrasensitive Memristive Aptasensor

Applications of Multi-Terminal Memristive Devices: A Review

Enhancing Delay-Driven LUT Mapping with Boolean Decomposition

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Image thresholding techniques for localization of sub-resolution fluorescent biomarkers

Emerging Technology Based Design of Primitives for Hardware Security

Superior sensing performance of multi-walled carbon nanotube-based electrodes to detect unconjugated bilirubin

Synchronization and Power Integrity Issues in 3-D ICs

Analytical Heat Transfer Model for Thermal Through-Silicon Vias

RM3 based logic synthesis

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Fast Procedures for the Electrodeposition of Platinum Nanostructures on Miniaturized Electrodes for Improved Ion Sensing

Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip

Processor Speed Control with Thermal Constraints

A Sound and Complete Axiomatization of Majority-n Logic

Routing Aware Switch Hardware Customization for Networks on Chips

Design Methods and Tools for 3D Integration