Publications by Jean-Michel Sallese

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This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just a ...

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor-insulator interface and the surrounding electro ...

A prospective study of the junctionless transistors (JLTs) scaling performances based both on TCAD and analytical evaluations of the intrinsic delay after considering on/off voltage constraints is proposed. The tradeoffs between speed and switching power p ...

This paper presents an equivalent electrical circuit for one dimensional substrate minority carriers spice simulation. The electrical circuit parameters are extracted from substrate meshing applying the finite difference method. This model is derived from ...

The Ward-Dutton (WD) partitioning scheme [IEEE Trans. Electron Devices, vol. ED-27, p. 1571, Aug. 1980] is used extensively to develop transient and high-frequency advanced compact models for MOSFET devices. Recently, it has been shown that WD partitioning ...

Solid-state qubits can be implemented with electrostatically confined quantum dots in semiconductors, allowing gate voltages to independently control the electrochemical potentials of each quantum dot. Quantum dots offer high levels of reliability and scal ...

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

The corrosion of iron or steel in contact with bentonite is a key factor affecting the long-term safety of radioactive waste disposal system. Previous studies focused on corrosion after long-term burial in compact bentonites, however, little work was dedicated to the corrosion of iron exposed to bentonite slurries, that can appear in case of fracture of the bentonite jacket separating steel from underground water. In this study, accelerated corrosion experiments were performed on pure iron in basic bentonit

The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and ...

Despite an evermore complete plethora of complex domain-specific semiempirical models, no succinct recipe for large-scale carbon nanotube electromechanical systems design has been formulated. To combine the benefits of these highly sensitive miniaturized m ...

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reporte ...

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

In this paper a floating body partially depleted SOI MOSFET used to measure light intensity using the transient charge pumping [1] is modeled through an equivalent electrical circuit. Essentially, photogenerated charges of the MOSFET are converted into a c ...

Metal–Insulator–Semiconductor High Electron Mobility Transistors (MIS-HEMTs) demonstrated to offer significant advantages for power electronics. The presence of an insulating layer beneath the gate enables operation at relatively high gate voltages, effectively mitigating conventional gate leakage issues. However, operation beyond the charge neutrality point leads to mobile charge accumulation under the gate insulator, resulting in the formation of a second channel. In this work, we present an explicit calc

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in th

Several Hall sensor configurations have been integrated in CMOS 0.35 mu m technology and analyzed in terms of offset at room temperature and offset drift. We searched for the best geometry that would minimize the offset and its corresponding drift. The tar ...

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout ...

Jean-Michel Sallese

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A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

On performance scaling and speed of junctionless transistors

Noise Modeling Methodologies in the Presence of Mobility Degradation and their Equivalence

Spice Simulation of Substrate Minority Carriers Propagation with Equivalent Electrical Circuit

Source–Drain Partitioning in MOSFET

Design space of quantum dot spin qubits

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Anodic dissolution mechanisms of iron in bentonite slurries

Analog RF and mm-Wave Design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA

System-Level Design Considerations for Carbon Nanotube Electromechanical Resonators

Spice Simulation of Passive Protection in Smart Power ICs

Submicrometer Organic Thin-Film Transistors: Technology Assessment Through Noise Margin Analysis of Inverters

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Electrical model of a single pixel SOI phototransistor relying on the transient charge pumping technique

Explicit Charge Density Modeling in MIS-HEMTs

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Smart Power IC simulation of substrate coupled current due to majority and minority carriers transports

Offset And Drift Analysis Of The Hall Effect Sensors. The Geometrical Parameters Influence

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors