Publications by Steve Tanner | EPFL Graph Search

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In this paper, we present the design, fabrication, and electrical characterization of a low-power microwave source for interrogation of cesium atomic hyperfine transition frequency using the coherent population trapping (CPT) technique. The 4.6-GHz frequen ...

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 Vrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 uW. The integrated offset compensation circuit makes the system less sensitive to mismatch and variations in the culture medium biasing voltage. A sample & hold (S&H) buffer stores the amplified input signals locally, thereby realising an electronic shutter function. This allow

The paper presents an analogue front-end and ADC integrated circuit for processing signals of sensors implanted into joint prosthesis. The circuit is designed to be operated with Wheatstone bridge sensors, such as strain gauges, pressure, Hall Effect, magneto-resistive sensors, etc. It performs sensor supply multiplexing, sensor signal amplification with chopper modulation, offset compensation and 14-bit analog to digital conversion in a single chip. It can operate simultaneously up to eight sensors at an o

This paper presents a new hybrid A/D conversion principle based on the combination of an incremental conversion for the most significant part of the result and on a cyclic conversion for the least significant part. The proposed approach exhibits a resoluti ...

The paper presents a CMOS sensor array for the detection of speckle movements, for applications requiring accurate movement tracking of arbitrary surfaces. The array is made of eight sensors incorporating each a spatial comb filter with a pitch of 2.8μm so ...

In this paper, a 4.6 GHz frequency synthesizer integrated circuit for Cesium-based miniature atomic clocks is presented. Based on a fractional-N phase-locked loop (PLL) with sigma-delta modulator, the chip features a frequency resolution below 10E-3 Hz at ...

In this work, we present the general concept of an instrumented smart knee prosthesis for in-vivo measurement of forces and kinematics. This system can be used for early monitoring of the patient after implantation and prevent possible damage to the prosth ...

We present a CMOS sensor for accurate tracking of speckle movements on arbitrary surfaces. The sensor is made of a pair of comb filters with a pitch of 5.6 mu m and decayed by 90 degrees to produce quadrature signals. The readout circuit is a 60 dB amplification chain with offset and KTC noise compensation. Integrated into a 180nm CMOS process, the sensor and readout circuit occupy an area of about 0.1 mm(2) and consume 24 mu W at full speed of 64 ksample/s. The direction and frequency of the quadrature sig

A prototype of a high-density multielectrode array for in vitro recording of electrogenic cell networks has been developed. On a surface of 1.92x1.92mm2, it includes 32x32 pixels with a dimension of 60x60µm2. For local amplification of the sensed extracell ...

A new bio-interface for active MEAs is presented in this paper. Unlike standard approaches that deposit MEA electrodes using post-processing of the integrated circuit, the proposed structure is based on Ti/Pt microelectrodes inserted by microfabrication in ...

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 μVrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 μW. The integrated of ...

In this work we present an instrumented smart knee prosthesis for in-vivo measurement of forces and kinematics. Studying the constraints, we designed minimal sensory systems to be placed in the polyethylene part of the prosthesis. The magnetic sensors and ...

This paper describes some of the design experiences achieved during the design, simulation and characterization of a Complementary Metal-Oxide Semiconductor (CMOS) LNA which has been designed for 24GHz and fabricated in a standard 0.180 µm technology. More ...

The Quantime project aims at developing a miniature atomic clock suited for the telecom market, requiring a wide operating temperature range (from -40 to +85°C), and a low production cost. The CPT (Coherent Population Trapping) technique for atomic interrogation is used for miniaturization and low power consumption. In the first phase of the project, the clock architecture was chosen, and the main sub-systems were developed. A clock breadboarding demonstrator was assembled and the measured Allan deviation o

The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in ...

The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal (LOCK), - a digital ...

In the paper, we present the design focused analysis of a power efficient cascode-compensated amplifier. The analysis, presented here, is much more intuitive than the reported work so far. Based on this analysis, an amplifier in UMC 0.18 µm technology is designed. Cascode compensation along with other power saving techniques results in a power efficient amplifier that achieves a relatively high figure of merit (1927 MHz.pF/mW). The designed amplifier is compared with the state of the art in the literature.

A new technique, Amplifier and Comparator Based Switched Capacitor (ACBSC) for low voltage switched cap circuits, is presented. ACBSC combines the recently introduced CBSC (comparator based switched capacitor circuit) with an amplifier. The current sources ...

This paper presents the design, realization and characterization of a new hybrid A/D converter based on a combined incremental and cyclic conversion. The proposed implementation offers a configurable resolution, and permits to share the same hardware for t ...

Steve Tanner

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CPT Cesium-Cell Atomic Clock Operation With a 12-mW Frequency Synthesizer ASIC

Low-Noise Amplifier with Sample & Hold for High-Density Stimulation and Recording of Neural Signals

An Analog Front-End and ADC Integrated Circuit for Implantable Force and Orientation Measurements in Joint Prosthesis

Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle

A speckle-based CMOS sensor array for arbitrary surface movement detection

A 4.6-GHz, 15-mW frequency synthesizer CMOS ASIC with milli-hertz frequency resolution for miniature atomic clocks

Instrumented Knee Prosthesis for Force and Kinematics Measurements

A speckle-based CMOS sensor for arbitrary surface movement detection with correlated double sampling and gain error correction

Fully differential low-noise amplifier with offset reduction for high-resolution neural signal recording

A glass-based, high density microelectrode array (MEA) with integrated CMOS amplification

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Instrumented Prosthesis for Knee Implants Monitoring

Design Experiences of a CMOS LNA for mm-waves

Quantime - A miniature cesium atomic clock using CPT technique for telecom application

A low power, low chip area decimation filter for Σ - Δ modulator for flywheel MEMS gyro realized in the CMOS 180 nm technology

Driven dual phase lock loop

Design And Analysis of A Power Efficient Cascode-Compensated Amplifier

A Novel 1V, 24μW, ∑∆ Modulator Using Amplifier & Comparator Based Switched Capacitor Technique, with 10-kHz Bandwidth and 64dB SNDR

Reply to "Comments on 'Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle'"

A 16-bit, 150-μW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme