Publications by Didier Bouvet | EPFL Graph Search

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI ...

In High Energy Physics (HEP) experiments it is a common practice to expose electronic components and systems to particle beams, in order to assess their level of radiation tolerance and reliability when operating in a radiation environment. One of the faci ...

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measur ...

Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technolo ...

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

This paper presents fabrication and RF characterization results of spiral inductors fabricated using a developed damascene-like thick-copper / polyimide process module. This module has low thermal budget and is compatible with current IC interconnect archi ...

Interest in PVDF-TrFE copolymers as ferroelectric material for Memory application is driven by the prospect of having low cost, low operating voltage and fully organic device. Some previous studies reported FET designs using copolymers [refs 1,2] but none ...

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8x10(14)cm(-3)) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of I-D(V-DS) are observed at high drain voltage (V-DS > 11V) on transistors that have short channel effects (L=0.9-10um). This is explained by the

In this work, highly scaled FinFETs (Fin Field Effect Transistors) are proposed as both sensing and circuit units of a lab-on-a-chip platform. The FinFET-based sensors with an HfO2 gate oxide demonstrate full pH-response with ΔVth ≈ 56 mV/pH. High readout ...

Interest in Ferroelectric FETs originates from their potential as non-volatile memories and, more recently, as abrupt switches. In this work, we focus on the role of the Curie temperature of the gate stack on the performance of Fe-FETs. The proposed study ...

In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to explo ...

A silicone-based one-transistor nonvolatile memory cell has been implemented by integration of a ferroelectric polymer gate on a standard n- type metal oxide semiconductor field effect transistor. The polarization reversal in the gate results in a stable a ...

This work presents a well-defined electronic device, namely a n-channel high-k dielectric FinFET (Fin Field Effect Transistor) as new label-free sensor for enhanced sensing integrated circuits. Metal gate FinFETs on bulk Si have been successfully electrica ...

This paper reports on an inductor fabrication method capable to deliver high quality factor (Q) and high self-resonance frequency (SRF) devices using quartz insulating substrates and thick high-conductivity copper lines. Inductors are key devices in RF circuits that, when fabricated on traditional semiconductor substrates, suffer from poor RF performances due to thin metallization and substrate related losses. Many previous works revealed that RF performances are strongly dependent on the limited metallizat

This work presents the technological development and characterization of n-channel fully depleted high-k dielectric FinFETs (Fin Field Effect Transistor) for applications in a liquid environment. Herein, we provide a systematic approach based on Finite Ele ...

We report on the temperature dependence of ferroelectric metal-oxide-semiconductor (MOS) transistors and explain the observed improved characteristics based on the dielectric response of ferroelectric materials close to the Curie temperature. The hysteretic current-voltage static characteristics of a fully depleted silicon-on-insulator transistor, with 40 nm vinylidene fluoride trifluorethylene, and 10 nm SiO2 gate stack, are measured from 300 to 400 K. In contrast with conventional MOS field effect transis

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonst ...

Fabrication of high-density ferroelectric memories requires the growth of the ferroelectric material on the drain contact metal. In standard 0.5 mum technology, tungsten plugs are applied to connect the drain contacts to the first metallization level. In this work, we investigated electrode systems to be applied between sputter deposited, ferroelectric PbZr0.35Ti0.65O3 (PZT) and tungsten. Besides the obvious barrier function of such an electrode system, the texture of the PZT is of interest as well. The rou

We report the significant improvement obtained by a non-uniform gate capacitance made by appropriate combination of high-k and low-k regions over the tunneling and the channel regions of a heterostucture TFET (called HKLKFFET). In addition to significantly enhanced ION and subthreshold swing, we find that this structure offers great improvements for the dynamic switching energy (66% saving) and propagation delay (similar to 3 x fast operation) compared to a heterostructure TFET (HeTFET) due to the reduction

Didier Bouvet

Chat with Graph Search

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

A BEAM PROFILE MONITOR FOR HIGH ENERGY PROTON BEAMS USING MICROFABRICATION TECHNIQUES

The high-mobility bended n-channel silicon nanowire transistor

Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Prospects for logic-on-a-wire

Fabrication and electrical characterization of high performance copper/polyimide inductors

1T Memory Cell Based on PVDF-TrFE Field Effect Transistor

Abrupt current switching due to impact ionization effects in Omega-MOSFET on low doped bulk silicon

Finfet with fully PH-responsive HfO2 as highly stable biochemical sensor

The Curie temperature as a key design parameter of ferroelectric Field Effect Transistors

Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs

Retention in nonvolatile silicon transistors with an organic ferroelectric gate

High-k dielectric FinFETs towards Sensing Integrated Circuits

High quality factor copper inductors integrated in deep dry-etched quartz substrates

Technological development of high-k dielectric FinFETs for liquid environment

Ferroelectric transistors with improved characteristics at high temperature

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Tungsten based electrodes for stacked capacitor ferroelectric memories

Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance