Lecture

Advanced MEMS Packaging

Graph Chat

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

In course

MICRO-534: Advanced MEMS & microsystems

In depth analysis of the operation principles and technology of advanced micro- and nanosystems. Familiarisation to their implementation into products and their applications. ...

Description

This lecture covers advanced techniques in MEMS packaging, including through-hole packages, ball grid arrays, flip-chip technology, surface mount packages, chip on board solutions, chip scale packaging, and failure analysis due to thermal stress and CTE mismatch. It also discusses microelectronic packaging components, such as die attach methods, soldering processes, and materials used. The instructor presents case studies of accelerometers and pressure sensors, highlighting the importance of careful gluing processes and material selection. Additionally, the lecture explores wafer-level packaging techniques, such as flip chip soldering and adhesive bonding, for MEMS devices, emphasizing the significance of hermetic sealing and stress control.

Instructors (2)

Niels Quack

Prof. Dr. Niels Quack received the M.Sc. degree from Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland, in 2005, and the Dr.Sc. degree from Eidgenössische Technische Hochschule Zürich (ETH), Zürich, Switzerland, in 2010. From 2011 to 2015, he was Postdoctoral Researcher and Visiting Scholar with the Integrated Photonics Laboratory, Berkeley Sensor and Actuator Center, University of California, Berkeley, CA, USA. From 2014 to 2015, he was Senior MEMS Engineer with Sercalo Microtechnology, Neuchâtel, Switzerland. He is currently an SNSF Assistant Professor with Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland. He has authored and co-authored more than 50 papers in leading technical journals and conferences. His research interests include photonic micro and nanosystems, with an emphasis on diamond photonics and silicon photonic MEMS. He is Steering Committee Member of the IEEE International Conference on Optical MEMS and Nanophotonics (OMN) and served as General Chair of the IEEE OMN 2018 and the Latsis Symposium 2019 on Diamond Photonics. He is a Senior Member of IEEE, Member of The Optical Society (OSA) and life member of SPIE.

Danick Briand

Expertise MEMS and MicrosystemsFlexible and Printed ElectronicsEnergy Harvesting and PowerMEMSSmart Sensing SystemsAdvanced Gas Sensing TechnologiesMicrofabrication and Printing technologiesMicrosystems Integration and Packaging Expertise MEMS and MicrosystemsFlexible and Printed ElectronicsEnergy Harvesting and PowerMEMSSmart Sensing SystemsAdvanced Gas Sensing TechnologiesMicrofabrication and Printing technologiesMicrosystems Integration and Packaging Mission Environmentally-friendly technology is a rapid

Official source

Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors

Related concepts (23)

Integrated circuit packaging

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board. In the integrated circuit industry, the process is often referred to as packaging. Other names include semiconductor device assembly, assembly, encapsulation or sealing.

Ball grid array

A ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits. BGA packages are used to permanently mount devices such as microprocessors. A BGA can provide more interconnection pins than can be put on a dual in-line or flat package. The whole bottom surface of the device can be used, instead of just the perimeter. The traces connecting the package's leads to the wires or balls which connect the die to package are also on average shorter than with a perimeter-only type, leading to better performance at high speeds.

Wafer-level packaging

Wafer-level packaging (WLP) is a process where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WSP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

Dual in-line package

In microelectronics, a dual in-line package (DIP or DIL) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits.

Pin grid array

A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package. PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP).

Related lectures (18)

Packaging of Intelligent Systems

Explores constraints in packaging systems, hierarchical assembly, chip packaging process, solder importance, and Pb-free solders.

Packaging of Intelligent Systems

Covers the packaging of intelligent systems, solder systems, major chip interconnection types, and packaging trends.

Infrared Photodetectors: Mercury Cadmium Telluride Technology

Covers the technology and applications of Mercury Cadmium Telluride photoconductors in infrared detection systems.

Chip Packaging Process Flow: Major Steps

Covers the major steps in chip packaging and the evolution of packaging technologies.

Molecular Transistors: Design and Simulation