Publication

Skew Variability in 3-D ICs with Multiple Clock Domains

Publications associées (27)

TDOA Source-Localization Technique Robust to Time-Synchronization Attacks

Jean-Yves Le Boudec, Marguerite Marie Nathalie Delcourt

In this paper, we focus on the localization of a passive source from time difference of arrival (TDOA) measurements. TDOA values are computed with respect to pairs of fixed sensors that are required to be accurately time-synchronized. This constitutes a we ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Time-Synchronization Attacks against Critical Infrastructures and their Mitigation

Marguerite Marie Nathalie Delcourt

This work focuses on the security of critical infrastructures against time-synchronization attacks (TSA). A TSA can impact any network that relies on the dynamic analysis of data, by altering the time synchronization between its nodes. Such attacked networ ...

EPFL2021

Time-Synchronization Attack Detection in Unbalanced Three-Phase Systems

Jean-Yves Le Boudec, Mario Paolone, Marguerite Marie Nathalie Delcourt, Gyorgy Miklos Dan

Phasor measurement units (PMU) rely on an accurate time-synchronization to phase-align the phasors and timestamp the voltage and current phasor measurements. Among the symmetrical components computed from the phasors in three-phase systems, the standard pr ...

2021

On Time Synchronization Issues in Time-Sensitive Networks with Regulators and Nonideal Clocks

Jean-Yves Le Boudec, Ludovic Bernard Gérard Thomas

Flow reshaping is used in time-sensitive networks (as in the context of IEEE TSN and IETF Detnet) in order to reduce burstiness inside the network and to support the computation of guaranteed latency bounds. This is performed using per-flow regulators (suc ...

Association for Computing Machinery2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Feasibility of Time Synchronization Attacks against PMU-based State-Estimation

Jean-Yves Le Boudec, Mario Paolone, Sergio Barreto Andrade, Marguerite Marie Nathalie Delcourt, Gyorgy Miklos Dan

The emerging measurement technology of phasor measurement units (PMUs) makes it possible to estimate the state of electrical grids in real-time, thus opening the way to new protection and control applications. PMUs rely on precise time synchronization, the ...

2019

A Sensor Network Architecture for Digital SiPM-Based PET Systems

Claudio Bruschini, Edoardo Charbon, Francesco Gramuglia

Digital silicon photo-multipliers (SiPMs) have emerged in the recent past as a viable low cost alternative to photomultiplier tubes in positron emission tomography systems, providing multiple timestamps, energy and scintillation coordinates at high spatial ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

The White Rabbit Time Synchronization Protocol for Synchrophasor Networks

Mario Paolone, Reza Razzaghi, Quentin Walger, Asja Derviskadic

Within the context of time dissemination techniques for power systems applications, the paper discusses the use of the White Rabbit (WR) protocol for synchrophasor networks. Specifically, the paper presents a Phasor Measurement Unit (PMU) integrating the W ...

2019

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Nicholas Alexander Preyss, Andrea Bonetti, Adam Shmuel Teman

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Yusuf Leblebici, Giovanni De Micheli, Alessandro Cevrero, Giulia Beanato, Kiarash Gharibdoust

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

Elsevier2016

ns-level time transfer over a microwave link using the PTP-WR protocol

Pierre-André Farine, Cyril Botteron, Jean-Pierre Aubry, Mathieu Paul Joseph Carlos Rico

Today it is possible to achieve sub-ns level time synchronization on a wireline network while only us-level synchronization can be achieved on a wireless (microwave) link. In this paper we will, first, study the performances of different time synchronizati ...

2015

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis, Wayne Burleson, Xifan Tang

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

An Enhanced Design Methodology for Resonant Clock Trees

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam, Xifan Tang

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

American Scientific Publishers2013

Method for estimating and correcting a drift between clocks of receiving transceiver and a corresponding emitting transceiver, and receive for implementing said method

Jean-Yves Le Boudec, Ruben Merz, Manuel Flury

Method for estimating and correcting a frequency offset between a local clock of a receiving transceiver and a remote clock of an emitting transceiver comprises receiving by said receiving transceiver, a signal emitted by the emitting transceiver, said sig ...

2013

Effects of Process Variations on 3-D Global Clock Distribution Networks

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Assoc Computing Machinery2012

Low-power clock distribution networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

2012

Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations

Hu Xu

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated se ...

EPFL2012

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Hu Xu, Vasileios Pavlidis, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012