Publications associées à Clock Distribution Networks in 3-D Integrated Systems

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

Front-End Circuits for Radiation-Hard Monolithic CMOS Sensors targeting High-Energy Physics Applications

Francesco Piro

Monolithic pixel sensors integrate the sensor matrix and readout in the same silicon die, and therefore present several advantages over the more largely used hybrid detectors in high-energy physics. They offer an easier detector assembly, lower cost, lower ...

EPFL2023

Sub-kHz-Linewidth External-Cavity Laser (ECL) With Si3N4 Resonator Used as a Tunable Pump for a Kerr Frequency Comb

Tobias Kippenberg, Junqiu Liu

Combining optical gain in direct-bandgap III-V materials with tunable optical feedback offered by advanced photonic integrated circuits is key to chip-scale external-cavity lasers (ECL), offering wideband tunability along with low optical linewidths. Exter ...

IEEE Institute of Electrical and Electronics Engineers2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Claudio Bruschini, Edoardo Charbon, Arin Can Ülkü, Andrei Ardelean, Paul Mos, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Rafael Medina Morillas

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

Low Noise Clock Generation: Modeling, Analysis and Implementation

Duygu Kostak

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

EPFL2021

A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Edoardo Charbon, Andrea Ruffino, Yatao Peng

An integrated circuit fabricated using industry-standard 40 nm complementary metal-oxide-semiconductor technology can combine silicon quantum devices, digital addressing and analogue multiplexed dispersive readout electronics. ...

NATURE PORTFOLIO2022

Integration of MEMS in Silicon Photonics

Alain Yuji Takabayashi

Like integrated electronics, integrated photonics such as Silicon Photonics benefit from increased device-density on a single chip. Silicon is an excellent material for integrated photonics because its high refractive index allows devices to be made small, ...

EPFL2021

On Time Synchronization Issues in Time-Sensitive Networks with Regulators and Nonideal Clocks

Jean-Yves Le Boudec, Ludovic Bernard Gérard Thomas

Flow reshaping is used in time-sensitive networks (as in the context of IEEE TSN and IETF Detnet) in order to reduce burstiness inside the network and to support the computation of guaranteed latency bounds. This is performed using per-flow regulators (suc ...

Association for Computing Machinery2020

Embedded Microchannel Cooling for High Power-Density GaN-on-Si Power Integrated Circuits

Elison de Nazareth Matioli, Reza Soleiman Zadeh Ardebili, Georgios Kampitsis, Remco Franciscus Peter van Erp, Luca Nela

In this work, we demonstrate a new thermal management approach for direct cooling of GaN-on-Si power integrated circuits (ICs), in which the Si substrate functions as a microfluidic heat sink, turning Si into a cost-effective, high thermal performance subs ...

IEEE2020

Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers

Serge Vaudenay, Francesco Regazzoni, Muhammed Fatih Balli, Subhadeep Banik

In CHES 2017, Jean et al. presented a paper on "Bit-Sliding" in which the authors proposed lightweight constructions for SPN based block ciphers like AES, PRESENT and SKINNY. The main idea behind these constructions was to reduce the length of the datapath ...

2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Toward ultra-low power design methodology for frequency generation in the IoT design space

Mathieu Yves Hervé Coustans

Today, the semiconductor industry is feeding our digital world with more and more data coming from compact embedded electronics that are monitoring our environment and feeding analytics for action. Interaction with our digital world is mostly achieved thro ...

EPFL2019

Fabrication and Characterisation of Epitaxial PMN-PT Nano-structures

Xiao Di

Downscaling of the minimal feature size, or the gate length has been the key for the exponential im-provement of the performance of the logic CMOS integrated circuits over the last six decades. How-ever, since about 2003, some fundamental limits in the dev ...

EPFL2019

Feasibility of Time Synchronization Attacks against PMU-based State-Estimation

Jean-Yves Le Boudec, Mario Paolone, Sergio Barreto Andrade, Marguerite Marie Nathalie Delcourt, Gyorgy Miklos Dan

The emerging measurement technology of phasor measurement units (PMUs) makes it possible to estimate the state of electrical grids in real-time, thus opening the way to new protection and control applications. PMUs rely on precise time synchronization, the ...

2019

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Fabio Sebastiano, Andrea Ruffino, Yatao Peng

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

An optical-frequency synthesizer using integrated photonics

Nicolas Volet, Tobias Kippenberg, Martin Hubert Peter Pfeiffer

Optical-frequency synthesizers, which generate frequency-stable light from a single microwave-frequency reference, are revolutionizing ultrafast science and metrology, but their size, power requirement and cost need to be reduced if they are to be more wid ...

2018

Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays

David Atienza Alonso, Ayse Kivilcim Coskun, Artem Andreev, Marina Zapater Sancho, Fulya Kaplan

Integrated flow cell array (FCA) is an emerging technology, targeting the cooling and power delivery challenges of modern 2D/3D Multi-Processor Systems-on-Chip (MPSoCs). In FCA, electrolytic solutions are pumped through microchannels etched in the silicon ...

2018

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Nicholas Alexander Preyss, Andrea Bonetti, Adam Shmuel Teman

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017