Clock Distribution Networks in 3-D Integrated Systems

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Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power, and a smaller footprint. Copper is the most commonly used conductor to ...

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic ...

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Clock Distribution Networks in 3-D Integrated Systems

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Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Method for speeding up boolean satisfiability

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment