Resource Sharing in Dataflow Circuits

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

Triangulation is an important task in the 3D reconstruction of computer vision. It seems simple to find the position of a point in 3D space when its 2D perspective projections in multi-view images are given and the corresponding camera projection matrices ...

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

A time-division multiplexing (TDM) digital channel coding scheme for wireline multi-drop interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TDM signaling reduces inter-symbol interference (ISI) an ...

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

A time-division multiplexing (TDM) digital channel coding scheme with inter-symbol interference (ICI) reduction property for multi-drop memory interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TD ...

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

This paper describes, develops, and validates SciLens, a method to evaluate the quality of scientific news articles. The starting point for our work are structured methodologies that define a series of quality aspects for manually evaluating news. Based on ...

Executing a dataflow program on a parallel platform requires assigning to each buffer a given size so that correct program executions take place without introducing any deadlock. Furthermore, in the case of dynamic dataflow programs, specific buffer size a ...

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

The limitations of clock frequency and power dissipation of deep sub-micron CMOS technology have led to the development of massively parallel computing platforms. They consist of dozens or hundreds of processing units and offer a high degree of parallelism ...

We experimentally achieve optical time multiplexing of multiple Nyquist channels. A single microresonator Kerr comb allows the generation of multiple Nyquist sinc shaped pulse trains. TDM of pulse trains are obtained through wavelength conversion inside a ...

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and ...

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

An application specific integrated circuit (ASIC) named ANTIGONE (ANalog To dIGital cONvErter) was designed in AMS 0.35 mu m technology to interface with four Ion-sensitive field-effect transistor (ISFET) sensors and perform real-time monitoring of some bi ...

Large dataflow designs appear as a result of functional specification of modern complex digital systems and/ or a result of unfolding and behavioral transformation of looped and branched programs. Since deep-submicron silicon technology provides large amou ...

Resource Sharing in Dataflow Circuits

Chattez avec Graph Search

Gain-Cell Embedded DRAMs: Modeling and Design Space

Multi-View Triangulation: Systematic Comparison and an Improved Method

Buffer Placement and Sizing for High-Performance Dataflow Circuits

A Time-Division Multiplexing Signaling Scheme for Low-Power Multi-Drop Memory Links

Combining Dynamic & Static Scheduling in High-level Synthesis

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Optimization Opportunities in RRAM-based FPGA Architectures

SciLens: Evaluating the Quality of Scientific News Articles Using Social Media and Scientific Literature Indicators

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Systematic Design Space Exploration of Dynamic Dataflow Programs for Multi-core Platforms

Experimental Generation and Time Multiplexing of Data-Carrying Nyquist Sinc Shaped Channels from a Single Microresonator-based Kerr Frequency Comb

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Generating Configurable Hardware from Parallel Patterns

Speculative Dataflow Circuits

Pattern-based fpga logic block and clustering algorithm

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines