Publication

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Publications associées (28)

Locking Made Easy

Rachid Guerraoui, Vasileios Trigonakis, Jelena Antic, Georgios Chatzopoulos

A priori, locking seems easy: To protect shared data from concurrent accesses, it is sufficient to lock before accessing the data and unlock after. Nevertheless, making locking efficient requires fine-tuning (a) the granularity of locks and (b) the locking ...

ACM Press2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The analysis of the trace graphs generated by dataflow program executions has been shown to be an effective tool for exploring and optimizing the design space of application programs on manycore/multicore platforms. In this work a new approach aiming at fi ...

Springer2015

Techniques for Detection, Root Cause Diagnosis, and Classification of In-Production Concurrency Bugs

Baris Can Cengiz Kasikci

Concurrency bugs are at the heart of some of the worst bugs that plague software. Concurrency bugs slow down software development because it can take weeks or even months before developers can identify and fix them. In-production detection, root cause ...

EPFL2015

Efficient Communication and Synchronization on Manycore Processors

Darko Petrovic

The increased number of cores integrated on a chip has brought about a number of challenges. Concerns about the scalability of cache coherence protocols have urged both researchers and practitioners to explore alternative programming models, where cache co ...

EPFL2015

Distributed Deconfliction Algorithm for Unmanned Aerial Vehicles with Limited Range and Field of View Sensors

Denis Gillet, Alcherio Martinoli, Steven Adriaan Roelofsen

This paper proposes a novel approach for collision avoidance between Unmanned Aerial Vehicles (UAVs) with limited range and field of view sensors. The algorithm is designed for unicycle vehicles that need to fly above a specific minimal speed to maintain f ...

2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

Marco Mattavelli, Claudio Paolo Alberti, Ab Al Hadi Bin Ab Rahman, Simone Casale Brunet

Minimizing buffer sizes of dynamic dataflow implementations without introducing deadlocks or reducing the design performance is in general an important and useful design objective. Indeed, buffer sizes that are too small causing a system to deadlock during ...

Ieee2014