Publication

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Publications associées (31)

Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing

Technology scaling has progressed to enable integrated circuits with extremely high density enabling systems of tremendous complexity with manageable power consumption. With the continuation of Moore's law for many years, electronic chips have been able to ...

EPFL2020

A Bin Encoding Training Of A Spiking Neural Network Based Voice Activity Detection

Milos Cernak, Giorgia Dellaferrera

Advances of deep learning for Artificial Neural Networks (ANNs) have led to significant improvements in the performance of digital signal processing systems implemented on digital chips. Although recent progress in low-power chips is remarkable, neuromorph ...

IEEE2020

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Mohamed Mostafa Sabry Aly, Halima Najibi, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

Energy Analysis of Lightweight AEAD Circuits

Andrea Felice Caforio, Muhammed Fatih Balli, Subhadeep Banik

The selection criteria for NIST's Lightweight Crypto Standardization (LWC) have been slowly shifting towards the lightweight efficiency of designs, given that a large number of candidates already establish their security claims on conservative, well-studie ...

2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Toward ultra-low power design methodology for frequency generation in the IoT design space

Mathieu Yves Hervé Coustans

Today, the semiconductor industry is feeding our digital world with more and more data coming from compact embedded electronics that are monitoring our environment and feeding analytics for action. Interaction with our digital world is mostly achieved thro ...

EPFL2019

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Matthias Bucher, Christian Enz, François Krummenacher, Christophe Lallement, Jean-Michel Sallese, Eric Vittoz, Wladyslaw Grabinski

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. T ...

IEEE2019

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

Topological Analog Signal Processing

Romain Christophe Rémy Fleury, Farzad Zangeneh Nejad

Analog signal processors have attracted a tremendous amount of attention recently, as they potentially offer much faster operation and lower power consumption than their digital versions. Yet, they are not preferable for large scale applications due to the ...

Nature Research2019

Ultrathin Junctionless Nanowire FET Model, Including 2-D Quantum Confinements

Farzan Jazaeri

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier ...

2019