Bio/CMOS interfaces and co-design

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

The Cleopatra ASIC is a 12-channel prototype ASIC for the readout of hydrogenated amorphous silicon sensors used for real-time dosimetry in radiation diagnostic and radiation therapy. The architecture is based on a current to frequency conversion based on ...

Monolithic integration of InSb on Si could be a key enabler for future electronic and optoelectronic applications. In this work, we report the fabrication of InSb metal-semiconductor-metal photodetectors directly on Si using a CMOS-compatible process known ...

Ferroelectric materials offer a broad range of application-relevant properties, including spontaneous polarization switchable by electric field. Archetypical representatives of this class of materials are perovskites, currently used in applications ranging ...

This paper presents an energy-efficient analog front-end circuit to monitor the pulmonary artery pressure (PAP) with piezoresistive pressure sensors. A low-power capacitively-coupled instrumentation amplifier (CCIA) is developed in order to boost the ampli ...

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate le ...

Nowadays the demand for communication over the wireless medium is significantly increasing, while the available wireless spectrum is already limited. In this thesis, we introduce new practical physical layer designs that employ node cooperation for more ef ...

A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the over ...

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 x 128 pixels and a p ...

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

In traditional cryptography, an attacker tries to infer a mathematical relationship between the inputs and outputs of a cryptosystem to recover secret information. With the advances in the theoretical basis of the cryptographic algorithms, this task became ...

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

This thesis presents the development of a low-power analog-to-digital converter (ADC) which is intended to be used in WPAN receivers. WPAN devices are usually mobile and, therefore, operate on batteries. This puts a strict limitation on the power dissipati ...

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...

has already been proven that analog emulation overcomes the speed limits of numerical simulators by means of a simple fixed-topology prototype. In order to enhance the modularity and the size of the emulated power system a dedicated platform based on a fie ...

Bio/CMOS interfaces and co-design

Chattez avec Graph Search

Cleopatra: a 12-channel recycling integrator ASIC for the readout of hydrogenated amorphous silicon detectors in radiotherapy dosimetry

Monolithic InSb nanostructure photodetectors on Si using rapid melt growth

Exploring ferroelectricity in HfO2-based thin films by tackling application-relevant challenges

A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System

Self-Heating Effects on the Thermal Noise of Deep Sub-Micron FD-SOI MOSFETs

Bringing physical layer cooperation closer to practical wireless systems

A 2.4-GHz low power polar transmitter for wireless body area network applications

Non-LUT field-programmable gate arrays

Architecture and applications of a high resolution gated SPAD image sensor

A New Basic Logic Structure for Data-Path Computation

Automated Side-Channel Vulnerability Discovery and Hardening : No-Cost Security Expertise for All

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Development of Reconfigurable Circuits for WPAN Applications

Towards Multi-Fabric 3D Integration Architectures

A 16-channel 220 µW neural recording IC with embedded delta compression

A mixed-signal platform dedicated to power system dynamic computation