Publications related to Bio/CMOS interfaces and co-design

Related publications (16)

Cleopatra: a 12-channel recycling integrator ASIC for the readout of hydrogenated amorphous silicon detectors in radiotherapy dosimetry

Nicolas Würsch, Jonathan Emanuel Thomet, Sylvain Dunand

The Cleopatra ASIC is a 12-channel prototype ASIC for the readout of hydrogenated amorphous silicon sensors used for real-time dosimetry in radiation diagnostic and radiation therapy. The architecture is based on a current to frequency conversion based on ...

2025

Monolithic InSb nanostructure photodetectors on Si using rapid melt growth

Anna Fontcuberta i Morral, Nicholas Paul Morgan

Monolithic integration of InSb on Si could be a key enabler for future electronic and optoelectronic applications. In this work, we report the fabrication of InSb metal-semiconductor-metal photodetectors directly on Si using a CMOS-compatible process known ...

ROYAL SOC CHEMISTRY2023

Exploring ferroelectricity in HfO2-based thin films by tackling application-relevant challenges

Matteo Cavalieri

Ferroelectric materials offer a broad range of application-relevant properties, including spontaneous polarization switchable by electric field. Archetypical representatives of this class of materials are perovskites, currently used in applications ranging ...

EPFL2021

A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System

Marco Mattavelli, Catherine Dehollain, Diego Ruben Barrettino, Kerim Türe, Mustafa Besirli

This paper presents an energy-efficient analog front-end circuit to monitor the pulmonary artery pressure (PAP) with piezoresistive pressure sensors. A low-power capacitively-coupled instrumentation amplifier (CCIA) is developed in order to boost the ampli ...

IEEE2019

Self-Heating Effects on the Thermal Noise of Deep Sub-Micron FD-SOI MOSFETs

Yusuf Leblebici

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate le ...

2017

Bringing physical layer cooperation closer to practical wireless systems

Emre Atsan

Nowadays the demand for communication over the wireless medium is significantly increasing, while the available wireless spectrum is already limited. In this thesis, we introduce new practical physical layer designs that employ node cooperation for more ef ...

EPFL2015

A 2.4-GHz low power polar transmitter for wireless body area network applications

Christian Enz, Vladimir Kopta

A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the over ...

Springer Verlag2014

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Architecture and applications of a high resolution gated SPAD image sensor

Edoardo Charbon, Claudio Bruschini, Samuel Burri, Francesco Regazzoni

We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 x 128 pixels and a p ...

Optical Soc Amer2014

A New Basic Logic Structure for Data-Path Computation

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

2014

Automated Side-Channel Vulnerability Discovery and Hardening : No-Cost Security Expertise for All

Ali Galip Bayrak

In traditional cryptography, an attacker tries to infer a mathematical relationship between the inputs and outputs of a cryptosystem to recover secret information. With the advances in the theoretical basis of the cryptographic algorithms, this task became ...

EPFL2014

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Davide Sacchetto, Shashi Kanth Bobba, Michele De Marchi

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

2013

Development of Reconfigurable Circuits for WPAN Applications

Alp Oguz

This thesis presents the development of a low-power analog-to-digital converter (ADC) which is intended to be used in WPAN receivers. WPAN devices are usually mobile and, therefore, operate on batteries. This puts a strict limitation on the power dissipati ...

EPFL2013

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

A 16-channel 220 µW neural recording IC with embedded delta compression

Yusuf Leblebici, Alexandre Schmid, Vahid Majidzadeh Bafar

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...

2011

A mixed-signal platform dedicated to power system dynamic computation

Maher Kayal, Sidi-Rachid Cherkaoui, Laurent Fabre, Ira Nagel, Cédric Meinen

has already been proven that analog emulation overcomes the speed limits of numerical simulators by means of a simple fixed-topology prototype. In order to enhance the modularity and the size of the emulated power system a dedicated platform based on a fie ...

IEEE2011