Publications associées à COCKTAIL: Multi-Core Co-Optimization Framework With Proactive Reliability Management

Publications associées (20)

LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Irem Boybat Kara, Flavio Ponzina, Joshua Alexander Harrison Klein, Yuxuan Wang, Abu Sebastian

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing ...

Institute of Electrical and Electronics Engineers (IEEE)2025

FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs

Paolo Ienne, Canberk Sönmez, Mohamed Mahfouz Ahmed Kotb Shahawy, Cemalettin Cem Belentepe

Shared Virtual Memory (SVM) is a mechanism that allows host-side applications and FPGA accelerators to access the same virtual address space. It enables accelerating algorithms with unpredictable memory access patterns by making transparent pointer sharing ...

Institute of Electrical and Electronics Engineers Inc.2024

AstriFlash: A Flash-Based System for Online Services

Lei Yan, Babak Falsafi, Siddharth Gupta, Mark Johnathon Sutherland, Yunho Oh, Lei Yan

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

2023

Friction and fracture: richness and complexity in dynamic rupture

Thibault Didier Roch

Understanding how things break and slide is of paramount importance to describe the dynamics of a broad range of physical systems. This includes day-to-day problems such as the breaking of a glass of wine or the sliding of skis on snow, but also engineerin ...

EPFL2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

2022

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Generating hardware and software for RISC-V cores generated with Rocket Chip generator

Endri Bezati

This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow desc ...

IEEE2021

Using an antenna as a tool for studying microturbulence and zonal structures in tokamaks with a global gyrokinetic GPU-enabled particle-in-cell code

Noé Thomas Elie Ohana

In order to get a better understanding of the interaction of plasma microinstabilities and associated turbulence with specific modes, an antenna is implemented in the global gyrokinetic Particle-In-Cell (PIC) code ORB5. It consists in applying an external ...

EPFL2020

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Andreas Peter Burg, Robert Giterman, Adam Shmuel Teman

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations und ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Accurate Emulation of Memristive Crossbar Arrays for In-Memory Computing

Irem Boybat Kara

In-memory computing is an emerging non-von Neumann computing paradigm where certain computational tasks are performed in memory by exploiting the physical attributes of the memory devices. Memristive devices such as phase-change memory (PCM), where informa ...

IEEE2020

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

David Atienza Alonso, Marina Zapater Sancho, Arman Iranfar, Luis Maria Costero Valero

The advent of online video streaming services along with the users' demand for high-quality contents require High Efficiency Video Coding (HEVC), which provides higher quality and compression at the cost of increased complexity. On one hand, HEVC exposes a ...

2020

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Andreas Peter Burg, Robert Giterman, Andrea Bonetti, Adam Shmuel Teman

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

David Atienza Alonso, Andreas Peter Burg, Miguel Peon Quiros, Martino Ruggiero, Andrea Bonetti, Flavio Ponzina, Benoît Walter Denkinger, Soumya Subhra Basu, Szabolcs Balási

Energy consumption is a significant obstacle to integrate deep learning into edge devices. Two common techniques to curve it are quantization, which reduces the size of the memories (static energy) and the number of accesses (dynamic energy), and voltage s ...

2020

Scaling Out Bioinformatics in the Data Center

Sam David Whitlock

Whole Genome Sequencing is a process in the field of bioinformatics that transforms biological samples of DNA into an electronic dataset of genetic bases. The process consists of two sequential components. First, the laboratory process of sequencing transf ...

EPFL2019

rstoolbox - a Python library for large-scale analysis of computational protein design data and structural bioinformatics

Bruno Emanuel Ferreira De Sousa Correia, Jaume Bonet Martinez, Zander Harteveld, Fabian Sesterhenn, Andreas Scheck

BackgroundLarge-scale datasets of protein structures and sequences are becoming ubiquitous in many domains of biological research. Experimental approaches and computational modelling methods are generating biological data at an unprecedented rate. The deta ...

2019

Hardware-conscious Query Processing in GPU-accelerated Analytical Engines

Anastasia Ailamaki, Periklis Chrysogelos, Panagiotis Sioulas

In order to improve their power efficiency and computational capacity, modern servers are adopting hardware accelerators, especially GPUs. Modern analytical DMBS engines have been highly optimized for multi-core multi-CPU query execution, but lack the nece ...

2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019