Publications associées à A Charge-Based Compact Model of Double Gate MOSFET

Publications associées (25)

Advanced analysis of fully-printed organic transistors platform for multi-ion detection in sweat

Danick Briand, Silvia Demuru, Xi Chen, Brince Paul Kunnel, Jaemin Kim

Organic electrochemical transistors are emerging as prominent biochemical sensors for multi-sensing, including ions, metabolites, hormones, or viruses. However, the implementation of the devices is mainly limited to a single-analyte detection and a single- ...

Elsevier BV2025

Deterministic grayscale nanotopography to engineer mobilities in strained MoS2 FETs

Giovanni Boero, Andras Kis, Jürgen Brugger, Georg Fantner, Nicola Marzari, Norma Rivano, Zhenyu Wang, Xia Liu, Ana Conde Rubio, Berke Erbas, Mitali Banerjee, Jin Jiang, Marcos Penedo Garcia

Field-effect transistors (FETs) based on two-dimensional materials (2DMs) with atomically thin channels have emerged as a promising platform for beyond-silicon electronics. However, low carrier mobility in 2DM transistors driven by phonon scattering remain ...

Nature Research2024

Trapping Layers Prevent Dopant Segregation and Enable Remote Doping of Templated Self-Assembled InGaAs Nanowires

Anna Fontcuberta i Morral, Nicholas Paul Morgan, Didem Dede, Valerio Piazza

Selective area epitaxy is a promising approach to definenanowirenetworks for topological quantum computing. However, it is challengingto concurrently engineer nanowire morphology, for carrier confinement,and precision doping, to tune carrier density. We re ...

AMER CHEMICAL SOC2023

Energy Efficient Sensing using Steep Slope Devices

Teodor Rosca

Today, we are witnessing the Internet of Things (IoT) revolution, which facilitates and improves our lives in many aspects, but comes with several challenges related to the technology deployment at large scales. Handling ever growing amounts of information ...

EPFL2022

Nonhysteretic Condition in Negative Capacitance Junctionless FETs

Jean-Michel Sallese, Farzan Jazaeri, Amin Rassekh

This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A hysteresis-free perovskite transistor with exceptional stability through molecular cross-linking and amine-based surface passivation

Mohammad Khaja Nazeeruddin, Peng Gao, Hobeom Kim

Organo-metal halide perovskite field-effect transistors present serious challenges in terms of device stability and hysteresis in the current-voltage characteristics. Migration of ions located at grain boundaries and surface defects in the perovskite film ...

ROYAL SOC CHEMISTRY2020

The influence of external electric fields on charge reorganization energy in organic semiconductors

Anne-Clémence Corminboeuf, Hongguang Liu

Charge reorganization energies (k) of inter-ring carbon-carbon (IRCC) bond connected conjugated polycyclics are shown to exhibit an electric-field-driven anisotropic character. An external electric field parallel to the IRCC linker(s) reduces k while the f ...

Royal Society of Chemistry2019

Functionality Enhanced Memories for Edge-AI Embedded Systems

David Atienza Alonso, Pierre-Emmanuel Julien Marc Gaillardon, William Andrew Simon, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

IEEE2019

900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain

Elison de Nazareth Matioli, Jun Ma, Minghua Zhu

In this letter, we present high-performance GaN-on-Si metal-oxide-semiconductor high electron mobility transistors with record reverse-blocking (RB) capability. By replacing the conventional ohmic drain with a hybrid tri-anode Schottky drain, a high revers ...

Institute of Electrical and Electronics Engineers2017

GaAs nanowires: from doping to plasmonic hybrid devices

Alberto Casadei

Semiconductor nanowires (NWs) are filamentary crystals with the diameter ranging from few tens up to few hundreds of nanometers. In the last 20 years, they have been intensively studied for the prospects that their unique quasi-one dimensional shape offers ...

EPFL2016

Emerging Technology Based Design of Primitives for Hardware Security

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon

Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their uniq ...

Assoc Computing Machinery2016

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Pietro Buccella, Camillo Stefanucci

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Leakage mechanisms and contact technologies in InAlN/GaN high electron mobility transistors

Lorenzo Lugani

GaN based electronic devices have progressed rapidly over the past decades and are nowadays starting to replace Si and classical III-V semiconductors in power electronics systems and high power RF amplifiers. AlGaN/GaN heterostructures have been, until rec ...

EPFL2015

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Fabrication and Optoelectronic Properties of Graphene Nanoribbons

Eberhard Ulrich Stützel

Graphene, a single layer of carbon atoms, exhibits excellent charge transport properties. However, due to the absence of a band gap in this two-dimensional carbon nanostructure, graphene-based field effect transistors cannot be turned off. One strategy to ...

EPFL2013

Low-cost, CMOS compatible, Ta2O5-based hemi-memristor for neuromorphic circuits

Giovanni De Micheli, Sandro Carrara

In the past, tantalum oxide devices have been used to create non-volatile digital memories, whilst neglecting the analogue memristive characteristics of such devices. In this Letter, it is shown that these devices can provide a low-cost, low-power solution ...

Institution of Engineering and Technology2012

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

Rafal Tomasz Dlugosz

An efficient transistor level implementation of a flexible, programmable Triangular Function (TF) that can be used as a Triangular Neighborhood Function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as Application-Specific Integrated Circu ...

2012

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011

Proposal and Performance Analysis of Normally Off n(++) GaN/InAlN/AlN/GaN HEMTs With 1-nm-Thick InAlN Barrier

Jean-François Carlin, Nicolas Grandjean, Eric Feltin

Design considerations and performance of n(++) GaN/InAlN/AlN/GaN normally off high-electron mobility transistors (HEMTs) are analyzed. Selective and damage-free dry etching of the gate recess through the GaN cap down to a 1-nm-thick InAlN barrier secures p ...

2010

Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

Mihai Adrian Ionescu, Katherine Boucart, Mohammad Najmzadeh

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the B ...

Elsevier2010