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Andreas Peter Burg

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Publications associées (211)

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming

This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbers ...

Institute of Electrical and Electronics Engineers2014

LLR-based Successive Cancellation List Decoding of Polar Codes

Mani Bastaniparizi, Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming

We present an LLR-based implementation of the successive cancellation list (SCL) decoder. To this end, we associate each decoding path with a metric which (i) is a monotone function of the path’s likelihood and (ii) can be computed efﬁciently from the chan ...

Ieee2014

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

Andreas Peter Burg, Carl Christian Sten Dominic Senning

In this paper, a VLSI implementation of a complete MIMO channel equalization ASIC based on lattice reduction-aided linear detection is presented. The architecture performs preprocessing steps at channel rate and low-complexity linear data detection at symb ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

2013

FireBird: PowerPC e200 Based SoC for High Temperature Operation

Thomas Maeder, Yusuf Leblebici, Pascal Andreas Meinerzhagen, Radisav Cojbasic, Andreas Peter Burg, Conor Joseph Slater, Ömer Cogal, Carl Christian Sten Dominic Senning

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

2013

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Ruben Braojos Lopez, Jeremy Hugues-Felix Constantin, Giovanni Ansaloni

Embedded biosignal analysis involves a considerable amount of parallel computations, which can be exploited by employing low-voltage and ultra-low-power (ULP) parallel computing architectures. By allowing data and instruction broadcasting, single instructi ...

2013

Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory

Paolo Ienne, Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg

2013

A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

Alessandro Cevrero, Andreas Peter Burg, Nicholas Alexander Preyss, Alexios Konstantinos Balatsoukas Stimming

We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable ...

IEEE2013

Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems

Andreas Peter Burg, Carl Christian Sten Dominic Senning

n this paper we present an architecture for an MMSE ﬁlter matrix computation unit for signal detection in MIMO-OFDM communication systems. We propose to compute the required matrix inverse based on a Cholesky decomposition, followed by a Gauss-Jordan matri ...

2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Pascal Andreas Meinerzhagen, Giovanni De Micheli, Davide Sacchetto, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

Impact of body biasing on the retention time of gain-cell memories

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consum ...

2013

Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications

Qiuting Huang, Andreas Peter Burg

Modern wireless communication systems require efficient channel equalizer implementations. This paper explores the design space of reduced-state sequence estimation (RSSE). We show how the concept of pre-computation can be applied to greatly reduce computa ...

IEEE2013

Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Martino Ruggiero, Jeremy Hugues-Felix Constantin

Personal health monitoring systems can offer a cost-effective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultra-low- power multi-core architecture featuring low-power cores, yet capable of ...

ACM and IEEE Press2012

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

Pascal Andreas Meinerzhagen, David Atienza Alonso, Ahmed Yasir Dogan, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Oskar Andersson

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ul ...

2012

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Madhura Purnaprajna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

Low Complexity Spectral Analysis of Heart-Rate-Variability through a Wavelet Based FFT

Andreas Peter Burg, Aviinaash Sankaranarayanan, Georgios Karakonstantis

In this paper, a low complexity system for spectral analysis of heart rate variability (HRV) is presented. The main idea of the proposed approach is the implementation of the Fast-Lomb periodogram that is a ubiquitous tool in spectral analysis, using a wav ...

2012

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Muhammad Umer Khalid

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, wh ...

Ieee2012

A Sub-VT 2T Gain-Cell Memory for Biomedical Applications

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman

All state-of-the-art subthreshold (sub-VT) memories are based on static bitcells, while the feasibility and limitations of dynamic bitcells operated in the sub-VT regime have not been studied yet. For the first time ever, we examine the sub-VT operation of ...

2012

Data Mapping for Unreliable Memories

Christoph Studer, Andreas Peter Burg, Georgios Karakonstantis

Future digital signal processing (DSP) systems must provide robustness on algorithm and application level to the presence of reliability issues that come along with corresponding implementations in modern semiconductor process technologies. In this paper, ...

2012

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Rashid Iqbal

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage ...

2012

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