Publications de Andreas Peter Burg

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This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on artificial intelligence for 5G and beyond 5G (B5G) with respect to implementations, algori ...

Designing energy-efficient cognitive radio transceivers requires joint optimization of medium access control and the physical layer implementation. In this paper we show an energy efficiency optimization strategy for IEEE 802.11n compliant transceivers in ...

This paper describes the implementation and performance analysis of the first fully operational beam-space multiple-input multiple-output (MIMO) antenna for the spatial multiplexing of two QPSK streams. The antenna is composed of a planar three-port radiat ...

Lattice-reduction (LR)-aided successive interference cancellation (SIC) is able to achieve close-to optimum error-rate performance for data detection in multiple-input multiple-output (MIMO) wireless communication systems. In this work, we propose a hardwa ...

LoRa is a chirp spread-spectrum modulation developed for the Internet of Things (IoT). In this work, we examine the performance of LoRa in the presence of both additive white Gaussian noise and interference from another LoRa user. To this end, we extend an ...

Neural networks have become indispensable for a wide range of applications, but they suffer from high computational- and memory-requirements, requiring optimizations from the algorithmic description of the network to the hardware implementation. Moreover, ...

PowerPC Architecture microcontrollers are commonly used in embedded applications. In this work we present FireBird, the first PowerPC based SoC for reliable operation beyond 200C. It is a significant challenge to design SoCs for reliable operation at high ...

In this work, we examine the performance of the LoRa chirp spread spectrum modulation in the presence of both additive white Gaussian noise and interference from another LoRa user. To this end, we extend an existing interference model to the more realistic ...

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MI ...

The de-facto standard decoding algorithm for polar codes, successive cancellation list (SCL) decoding, is a breadth-first search algorithm. By keeping a list of candidate codewords, SCL decoding improves the performance as the list size L increases. Howeve ...

Polar codes are one of the most recent advancements in coding theory and they have attracted significant interest. While they are provably capacity achieving over various channels, they have seen limited practical applications. Unfortunately, the successiv ...

This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme is based on Brun's algorithm for finding integer relations. We analyze its high-level ar ...

A complete digital synchronization architecture for an IEEE 802.11ad compliant 60 GHz receiver is presented. The characteristics of mmWave systems require a holistic view on the problem of parameter estimation, such that not each parameter is dealt with on ...

An extension of approximate computing, significance-based computing exploits applications' inherent error resiliency and offers a new structural paradigm that strategically relaxes full computational precision to provide significant energy savings with min ...

Low power wide area network technologies (LPWANs) are attracting attention because they fulfill the need for long range low power communication for the Internet of Things. LoRa is one of the proprietary LPWAN physical layer (PHY) technologies, which provid ...

In this work, we propose an ultra-low power highly configurable analog/mixed-signal (AMS) processor as part of a smart RF signal detection and recognition system focusing on the ISM band. The analog feature extraction approach reduces power consumption and ...

Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-V T analysis methods are reviewed, both of which a ...

LoRa is currently one of the most widely used low-power wide-area network (LPWAN) technologies. The physical layer leverages a chirp spread spectrum modulation to achieve long-range communication with low power consumption. Synchronization at long distance ...

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

Andreas Peter Burg

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Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations

Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers

Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments

VLSI Implementation of a Low-Complexity LLL Lattice Reduction Algorithm for MIMO Detection

On the Error Rate of the LoRa Modulation With Interference

Lupulus: A Flexible Hardware Accelerator For Neural Networks

FireBird: PowerPC e200 Based SoC for High Temperature Operation

LoRa Symbol Error Rate Under Non-Aligned Interference

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization

List Ordered Statistics Decoders for Polar Codes

Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes

VLSI implementation of a lattice-reduction algorithm for multi-antenna broadcast precoding

Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems

Energy Efficiency through Significance-Based Computing

Lora Digital Receiver Analysis And Implementation

An Ultra Low Power Analog/Mixed-Signal Processor for a Smart RF Signal Classification System in the ISM Band

Synthesis strategies for sub-VT systems

LoRa Fine Synchronization with Two-Pass Time and Frequency Offset Estimation

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS