Publications de Babak Falsafi | EPFL Graph Search

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Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...

Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

Multi-pod systolic arrays are emerging as the architecture of choice in DNN inference accelerators. Despite their potential, designing multi-pod systolic arrays to maximize effective throughput/Watt-i.e., throughput/Watt adjusted when accounting for array ...

We propose a power-efficient many-core server-on-chip system with 3D-stacked Wide I/O DRAM targeting cloud workloads in datacenters. The integration of 3D-stacked Wide I/O DRAM on top of a logic die increases available memory bandwidth by using dense and f ...

Despite the natural parallelism across lookups, performance of distributed key-value stores is often limited due to load imbalance induced by heavy skew in the popularity distribution of the dataset. To avoid violating service level objectives expressed in ...

This article presents position statements and a question-and-answer session by panelists at the Fourth Workshop on Computer Architecture Research Directions. The subject of the debate was the use of field-programmable gate arrays versus GPUs in datacenters ...

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memory-side processing units (MPUs) ...

Data transformer apparatus comprising at least a dispatcher module (D), a reader module (R), a converter module (C) and a writer module (W). The dispatcher module (D) is configured to: receive a data transformation request (DTR) including: a first informat ...

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache archit ...

This column introduces seven invited position papers about the challenges and opportunities in near-data processing. "Near-Memory Data Services" by Babak Falsafi, "Automata Processing: The Memory Is the Processor!" by Mircea Stan, Kevin Skadron, "Overcomin ...

Modern online services are shifting away from monolithic applications to loosely-coupled microservices because of their improved scalability, reliability, programmability and development velocity. Microservices communicating over the datacenter network req ...

Conventional directory coherence operates at the finest granularity possible, that of a cache block. While simple, this organization fails to exploit frequent application behavior: at any given point in time, large, continuous chunks of memory are often ac ...

Commercial server applications remain memory bound on modern multiprocessor systems because of their large data footprints, frequent sharing, complex non-strided access patterns, and long chains of dependant misses. To improve memory system performance des ...

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

Locks are a natural place for improving the energy efficiency of software systems. First, concurrent systems are mainstream and when their threads synchronize, they typically do it with locks. Second, locks are well-defined abstractions, hence changing the ...

Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of integration have enabled the advent of chip multiprocessors and ...

Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming replays previously observed miss sequences to eliminate long chains of depende ...

The authors propose a high-capacity cache architecture that leverages emerging high-bandwidth memory modules. High-capacity caches capture the secondary data working sets of scale-out workloads while uncovering significant spatiotemporal locality across da ...

Modern in-memory services rely on large distributed object stores to achieve the high scalability essential to service thousands of requests concurrently. The independent and unpredictable nature of incoming requests results in random accesses to the objec ...

A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each l ...

Babak Falsafi

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Confluence: unified instruction supply for scale-out servers

SecureCells: A Secure Compartmentalized Architecture

Scale-out Systolic Arrays

Thermal Characterization of Cloud Workloads on a Power-Efficient Server-on-Chip

An Analysis of Load Imbalance in Scale-out Data Serving

FPGAs versus GPUs in Data centers

Near-Memory Address Translation

Data transformer apparatus

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

Near-Memory Data Services

Optimus Prime: Accelerating Data Transformation in Servers

Multi-Grain Coherence Directory

Temporal streams in commercial server applications

AstriFlash: A Flash-Based System for Online Services

Unlocking Energy

Database Servers on Chip Multiprocessors: Limitations and Opportunities

Spatio-Temporal Memory Streaming

Fat Caches For Scale-Out Servers

SABRes: Atomic Object Reads for In-Memory Rack-Scale Computing

Atomic object reads for in-memory rack-scale computing