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Babak Falsafi

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Publications associées (89)

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Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

An Analysis of Database System Performance on Chip Multiprocessors

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of integration have enabled the advent of chip multiprocessors and ...

2007

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland

Modern online services come with stringent quality requirements in terms of response time tail latency. Because of their decomposition into fine-grained communicating software layers, a single user request fans out into a plethora of short, μs-scale RPCs, ...

ACM2019

Last-touch correlated data streaming

Babak Falsafi, Michael Ferdman

Recent research advocates address-correlating predictors to identify cache block addresses for prefetch. Unfortunately, address-correlating predictors require correlation data storage proportional in size to a program's active memory footprint. As a result ...

2007

Mitigating Load Imbalance in Distributed Data Serving with Rack-Scale Memory Pooling

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic, Dmitrii Ustiugov

To provide low-latency and high-throughput guarantees, most large key-value stores keep the data in the memory of many servers. Despite the natural parallelism across lookups, the load imbalance, introduced by heavy skew in the popularity distribution of k ...

2019

Scale-Out NUMA

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

Emerging datacenter applications operate on vast datasets that are kept in DRAM to minimize latency. The large number of servers needed to accommodate this massive memory footprint requires frequent server-to-server communication in applications such as ke ...

2014

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Javier Picorel Obando, Alexandros Daglis, Mark Johnathon Sutherland, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

Shore-MT: A Scalable Storage Manager for the Multicore Era

Anastasia Ailamaki, Babak Falsafi, Frederick Ryan Johnson, Ippokratis Pandis

Database storage managers have long been able to efficiently handle multiple concurrent requests. Until recently, however, a computer contained only a few single-core CPUs, and therefore only a few transactions could simultaneously access the storage manag ...

ACM2009

Equinox: Training (for Free) on a Custom Inference Accelerator

Babak Falsafi, Martin Jaggi, Mario Paulo Drumond Lages De Oliveira, Ahmet Caner Yüzügüler, Arash Pourhabibi Zarandi, Louis Coulon

DNN inference accelerators executing online services exhibit low average loads because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming idle inference cycles is difficult as other workloads can not execute on a ...

ACM2021

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

BuMP: Bulk Memory Access Prediction and Streaming

Babak Falsafi, Boris Robert Grot, Javier Picorel Obando, Stavros Volos

With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

Giovanni De Micheli, Babak Falsafi, Boris Robert Grot, Ciprian Seiculescu, Stavros Volos, Naser Khosro Pour

Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...

2012

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs

Babak Falsafi

Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is limited throughput when simulating large multiprocessor systems with hundred ...

2009

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors

Babak Falsafi

Distributed shared-memory (DSM) multi- processors provide a scalable hardware platform, but lack the necessary redundancy for mainframe-level reliability and availability. Chip-level redundancy in a DSM server faces a key challenge: the increased latency t ...

2009

Scale-out non-uniform memory access

Babak Falsafi, Edouard Bugnion, Boris Robert Grot, Alexandros Daglis, Stanko Novakovic

A computing system that uses a Scale-Out NUMA (“soNUMA”) architecture, programming model, and/or communication protocol provides for low-latency, distributed in-memory processing. Using soNUMA, a programming model is layered directly on top of a NUMA memor ...

2015

The NEBULA RPC-Optimized Architecture

Babak Falsafi, Alexandros Daglis, Siddharth Gupta, Mark Johnathon Sutherland

Large-scale online services are commonly structured as a network of software tiers, which communicate over the datacenter network using RPCs. Ongoing trends towards software decomposition have led to the prevalence of tiers receiving and generating RPCs wi ...

2020

Analog Neural Networks with Deep-submicron Nonlinear Synapses

Pascal Frossard, Babak Falsafi, Mario Paulo Drumond Lages De Oliveira, Firat Çelik, Ahmet Caner Yüzügüler

Deep neural network (DNN) inference tasks are computationally expensive. Digital DNN accelerators offer better density and energy efficiency than general-purpose processors but still not sufficient to be deployable on resource-constrained settings.Analog c ...

2019

Temporal instruction fetch streaming

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...

2008

Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman, Yusuf Onur Koçberber, Adrian Daniel Popescu, Stavros Volos, Dorde Jevdic, Ilknur Cansu Kaynak, Al Mutaz Adileh, Mohammad Alisafaee

Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and calling for improvements in the computational ...

2012