Philip Brisk

Cette personne a quitté l’EPFL

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Publications associées (34)

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Compressor Tree Synthesis on Commercial High-Performance FPGAs

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and ...

2011

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Philip Brisk, Ties Jan Henderikus Kluter

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Philip Brisk, Mirjana Stojilovic

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Using 3D Integration Technology To Realize Multi-Context Fpgas

Yusuf Leblebici, Paolo Ienne, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar, Maurizio Skerlj

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Paolo Ienne, Philip Brisk

The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to b ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Progressive decomposition: A heuristic to structure arithmetic circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

2007

Generalized programmable counter arrays

Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel coun ...

2014

Philip Brisk

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Compressor Tree Synthesis on Commercial High-Performance FPGAs

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Using 3D Integration Technology To Realize Multi-Context Fpgas

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Progressive decomposition: A heuristic to structure arithmetic circuits

Generalized programmable counter arrays

From C to elastic circuits

Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions

Thermal-Aware Data Flow Analysis

Design Space Exploration for Field Programmable Compressor Trees

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow