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Philip Brisk

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Related publications (34)

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Using 3D Integration Technology To Realize Multi-Context Fpgas

Paolo Ienne, Yusuf Leblebici, Maurizio Skerlj, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Paolo Ienne, Philip Brisk

The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to b ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Thermal-Aware Data Flow Analysis

David Atienza Alonso, Philip Brisk, José Luis Ayala Rodrigo

IEEE Press2009

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

2009

Scalable and Low Cost Design Approach for Variable Block Size Motion Estimation (VBSME)

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Variable block size motion estimation (VBSME) in state-of-the-art video coding standards is one of the key features which improves the coding efficiency significantly compared to the previous standards. VBSME hardware design is a challenging task due to it ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...

2008

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Philip Brisk, Panagiotis Athanasopoulos, Alessandro Cevrero, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

Fast, quasi-optimal, and pipelined instruction-set extensions

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, the AFUs must satisfy certain constraints in terms of read and write ports betw ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

A Novel FPGA Logic Block for Improved Arithmetic Performance

Philip Brisk, Hadi Parandeh Afshar

To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed loca ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2008

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Philip Brisk

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Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Using 3D Integration Technology To Realize Multi-Context Fpgas

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Thermal-Aware Data Flow Analysis

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow

Scalable and Low Cost Design Approach for Variable Block Size Motion Estimation (VBSME)

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Fast, quasi-optimal, and pipelined instruction-set extensions

A Novel FPGA Logic Block for Improved Arithmetic Performance

Design Space Exploration for Field Programmable Compressor Trees

Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions

Progressive decomposition: A heuristic to structure arithmetic circuits