Publications de Luca Benini | EPFL Graph Search

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Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in ...

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both p ...

3D ultrasound imaging is quickly becoming a refer- ence technique for high-quality, accurate, expressive diagnostic medical imaging. Unfortunately, its computation requirements are huge and, today, demand expensive, power-hungry, bulky processing resources ...

In the last years, remote health monitoring is becoming an essential branch of health care with the rapid development of wearable sensors technology. To meet the demand of new more complex applications and ensuring adequate battery lifetime, wearable senso ...

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the ne ...

Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded pla ...

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

The authors of a Computer article from 2002 reflect on their proposal to use networks on chips to address scalable communications on silicon VLSI chips. ...

Chemiluminescence, i.e. the emission of light from a chemical reaction, offers interesting opportunities for developing point-of-care biosensors. However, commercially available systems are expensive, bulky, and primarily addressed to laboratory usage. The ...

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies base ...

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or a ...

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

Luca Benini

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A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Guarantees

NoC Design and Implementation in 65 nm Technology

Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging

Modular Design and Optimization of Biomedical Applications for Ultra-Low Power Heterogeneous Platforms

Diseño de redes en chip de propósito específico con información de rutado físico

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Networks on Chips: 15 Years Later

Cancer marker detection in human serum with a point-of-care low-cost system

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Improving the Fault Tolerance of Nanometric PLA Designs

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

A Novel Approach for Network on Chip Emulation

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Bringing NoCs to 65nm