Seyed Armin Tajalli

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Publications associées (48)

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Eric Vittoz, Yusuf Leblebici, Seyed Armin Tajalli

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

2007

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

2007

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption ...

IEEE Service Center2007

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition ...

IEEE2006

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are d ...

IEEE2006

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

IEEE2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005

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