Seyed Armin Tajalli

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Publications associées (48)

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A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

Yusuf Leblebici, Seyed Armin Tajalli, Gain Kim, Kiarash Gharibdoust

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rath ...

Ieee2016

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are d ...

IEEE2006

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Yusuf Leblebici, Seyed Armin Tajalli, Zeynep Toprak Deniz, Omer Can Akgun, Thomas Liechti

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

Ultra-Low Power 32-bit Pipelined Adder Using Subthreshold Source-Coupled Logic with 5fJ/stage PDP

Yusuf Leblebici, Seyed Armin Tajalli

This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible ...

2009

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Yusuf Leblebici, Seyed Armin Tajalli, Paul Victor Georges Muller

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition ...

IEEE2006

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Yusuf Leblebici, Seyed Armin Tajalli, Eric Vittoz

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

2007

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

Yusuf Leblebici, Seyed Armin Tajalli

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...

NORCHIP2008

Improving the power-delay performance in subthreshold source-coupled logic circuits

Yusuf Leblebici, Seyed Armin Tajalli

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved pow ...

Springer2009