Publications de Yusuf Leblebici

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The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

We develop a model for carrier generation by impact ionization in graphene, which shows that this effect is non-negligible because of the vanishing energy gap, even for carrier transport in moderate electric fields. Our theory is applied to graphene field ...

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

Image processing and computer vision algorithms extensively use projections, such as homography, as one of the processing steps. Systems for homography calculation usually observe homography as an inverse problem and provide an exact solution. However, the ...

This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimental flex ...

Omnidirectional stereoscopy and depth estimation are complex problems of image processing to which the Panoptic camera offers a novel solution. The Panoptic camera is a biologically-inspired vision sensor made of multiple cameras. It is a polydioptric syst ...

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

The floating gate (FG) potential VFG in a non–volatile flash memory (NVM) device is the main parameter controlling the behavior of the cell. A common technique to model VFG is based on the calculation of the coupling coefficients between all the terminals ...

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and dela ...

A time-division multiplexing (TDM) digital channel coding scheme with inter-symbol interference (ICI) reduction property for multi-drop memory interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TD ...

Label–free DNA detection is of crucial role to when developing point-of-care biochips to be used in personalized therapy. Capacitance detection is a promising technology for label-free DNA detection. However, data published in literature often show evident ...

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to ...

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Drones have become steadily affordable, which raises privacy and security concerns as well as interest in drone detection systems. On the other hand, drone detection is a challenging task due to small dimensions of drones, difficulty of long-distance detec ...

A multiphonon-assisted model included in a Poisson-Schroedinger solver has been applied to the calculation of the capture/emission trapping rates of CMOS oxide interface defects. The dependencies of trap capture cross-sections with trap energy, depth, appl ...

The architecture of an integrated Hamming artificial neural network, and its use as a versatile signal/image processing circuit is presented. The circuit operation relies oil the charge-based processing of sum-of-products terms, complemented with digital p ...

Si nanowire (NW) stacks are fabricated by utilizing the scalloping effect of inductively coupled plasma deep reactive ion etching. When two etch windows are brought close enough, scallops from both sides will ideally meet along the dividing centerline of t ...

Vertically stacked nanowire FETs (NWFETs) with gate-all-around structure are the natural and most advanced extension of FinFETs. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., the device shows n- and p-type characteristics sim ...

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconn ...

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted si ...

Yusuf Leblebici

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Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Impact Ionization and Carrier Multiplication in Graphene

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Reconfigurable Forward Homography Estimation System for Real-Time Applications

Real-time high-sensitivity impedance measurement interface for tethered BLM biosensor arrays

Enhanced Omnidirectional Image Reconstruction Algorithm and its Real-Time Hardware

Prospects for logic-on-a-wire

Analytical and compact models of the ONO capacitance in embedded non-volatile flash devices

Dynamic Thermal Management in 3D Multicore Architectures

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

New probe immobilizations by lipoate-diethalonamine or ethylene-glycol molecules for capacitance DNA chip

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Real-time high-resolution omnidirectional imaging platform for drone detection and tracking

Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model

CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications

Monolithic Integration of Silicon Nanowires With a Microgripper

Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold