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This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustra

The sensitivity of RF CMOS receivers using a direct conversion or a low-IF architecture is strongly affected by flicker noise. This paper gives theoretical guidelines to predict the flicker noise in Gilbert-cell mixers. The conversion gain, the equivalent input and output noise, and the effect of the pole at the single internal RF node are discussed. For the first time, results which are valid in all modes of operation are given. Such complete results are required for some ultra low-power and low-voltage ap

In the first part of the paper, also in this issue of the JOURNAL, the design of the frequency synthesizer and receiver section of an FSK transceiver was described. It operates in the 434-MHz ISM (Industrial, Scientific, Medical) band and is realized in a standard digital 0.5-μm CMOS process. This companion paper focuses on the realization of the transmitter section. It includes a power amplifier, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation.

New applications such as wireless integrated network sensors (WINS) require radio-frequency transceivers consuming very little power compared to usual mainstream applications, while still working in the ultra-high-frequency range. For this kind of applications, the LC-tank-based local oscillator remains a significant contributor to the overall receiver power consumption. This statement motivates the development of good on-chip varactors available in a standard process. This paper describes and compares the

This paper presents three basic approaches for determining the transient stability of a power network by using an analog VLSI chip for simulating or emulating the system behavior. The main advantages of using this method are the much shorter computation time and lower complexity compared to the currently used methods that are based on numerical calculations or discrete analog simulators

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing ...

This paper suggests several approaches for determining the transient stability of a power network by using an analog VLSI chip for simulating the system behavior. The main advantages of using this method are the much shorter computation time and lower complexity compared to the currently used methods, which are based on numerical calculations or discrete analog emulators

This paper suggests several approaches for determining the transient stability of a power network by using an analog VLSI chip for simulating the system behavior. The main advantages of using this method are the much shorter computation time and lower complexity compared to the existing methods that are based on numerical calculations or discrete analog emulators

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can ...

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

In this paper a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The ...

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

Eric Vittoz

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Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Architecture and Receiver

An Analysis of Flicker Noise Rejection in Low-Power and Low-Voltage CMOS Mixers

An Ultralow-Power UHF Transceiver Integrated in a Standard Digital CMOS Process: Transmitter

Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process

Analog VLSI solution to the stability study of power networks

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Approaches for analog VLSI simulation of the transient stability of large power networks

On-chip transient stability simulator, 104 times faster than real time

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

Configurable on-line global energy optimization in multi-core embedded systems using principles of analog computation

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

A Basic Property of MOS Transistors and its Circuit Implications

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

EKV Model of the MOS Transistor

A 1V, 434 MHz FSK Transceiver, Consuming 1mW in Receive Mode, and Fully Integrated in a Standard Digital CMOS Process

Addition to "An Analysis of Flicker Noise Rejection in Low-Power and Low-Voltage CMOS Mixers"