Publications de Paolo Ienne | EPFL Graph Search

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This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

NOVELTY - The method involves traversing a tree of potential complex computer operations; and pruning the tree for optimality under constraints. The optimality comprises maximization of a function of merit. The constraints comprise a convexity constraint, a maximum-input-multiplicity constraint, or a maximum-output-multiplicity constraint. USE - For determining complex computer operation for computer application. ADVANTAGE - Enhances processing performance by automatically forming extensions from high-level

Networks-on-chip provide an elegant framework to efficiently reuse predesigned cores. However, reuse of cores is jeopardized by new deep sub-micron noise effects that challenge the reliability of CMOS technology. Moreover, noise margins are further reduced as supply voltages scale down. We advocate that self-calibrating techniques will be needed to maintain an acceptable design trade-off between energy, performance, and reliability. As a result, self-calibrating techniques have to be integrated within netwo

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primari

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

We develop a channel model for errors originated from over-aggressive operation of a communication link. Such a situation arises in the context of on-chip self-calibrating communication, where a link controller has to determine adaptively the operating voltage and frequency. Based on this channel model, we derive an analytical expression for the undetection error probability of linear codes, and alternating-phase codes, the latter being an extension of the former.

Dataflow circuits have been studied for decades as a way to implement both asynchronous and synchronous designs, and, more recently, have attracted attention as the target of high-level synthesis (HLS) compilers. Yet, little is known about mechanisms to sy ...

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; ho ...

Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition: however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable Compressor Tree (FPCT

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimising this performance gap by using fixed, fine-grained, non-programmable logic structures in place o ...

Classifying functions according to some common properties into libraries of functions is an important step in many logic synthesis and technology mapping algorithms used in FPGA design flows. NPN classification is one of the frequently used classifications ...

Enumerating simple cycles has important applications in computational biology, network science, and financial crime analysis. In this work, we focus on parallelising the state-of-the-art simple cycle enumeration algorithms by Johnson and Read-Tarjan along ...

We address the quantitative comparison of two basic connection schemes for on-chip communication, connection-oriented and connection-less, regarding their enforcement of a defined Quality-of-Service for the communication. For such comparison, we have built ...

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and ...

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

Paolo Ienne

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Using 3D Integration Technology To Realize Multi-Context Fpgas

ShiDianNao: shifting vision processing closer to the sensor

Automated Instruction-Set Extension

Self-Calibrating Networks-On-Chip

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Non-LUT field-programmable gate arrays

Undetection error probability of linear and alternating-phase codes over the timing error channel

ElasticMiter: Formally Verified Dataflow Circuit Rewrites

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs

Arithmetic Optimization for Custom Instruction Set Synthesis

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Fast Hierarchical NPN Classification

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip

Resource Sharing in Dataflow Circuits

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Compressor Tree Synthesis on Commercial High-Performance FPGAs

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs