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Paolo Ienne

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Publications associées (132)

Fast, Nearly Optimal ISE Identification with I/O Serialization through Maximal Clique Enumeration

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with instruction set extensions (ISEs) that exec ...

2010

On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis

Paolo Ienne, Philip Brisk

The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to b ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Paolo Ienne, Yusuf Leblebici, Zeynep Toprak Deniz, Francesco Regazzoni

This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency ...

2009

MPSoC Design using Application-Specific Architecturally Visible Communication

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide high-throughput communication for streaming applications. Producer/consumer relationships map poorly onto cache-based MPSo ...

Springer-Verlag2009

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

From gates to multi-processors learning systems hands-on with FPGA4U in a computer science programme

René Beuchat, Paolo Ienne, Claudio Favi, Xavier Jimenez

ACM Press2009

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Using 3D Integration Technology To Realize Multi-Context Fpgas

Paolo Ienne, Yusuf Leblebici, Maurizio Skerlj, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The interference graph for a procedure in Static Single Assignment (SSA) Form is chordal. Since the k-colorability problem can be solved in polynomial-time for chordal graphs, this result has generated interest in SSA-based heuristics for spilling and coal ...

Springer US2009

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Scalable and Low Cost Design Approach for Variable Block Size Motion Estimation (VBSME)

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Variable block size motion estimation (VBSME) in state-of-the-art video coding standards is one of the key features which improves the coding efficiency significantly compared to the previous standards. VBSME hardware design is a challenging task due to it ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

2009

Special Section on Application Specific Processors

Paolo Ienne

2008

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Philip Brisk, Panagiotis Athanasopoulos, Alessandro Cevrero, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

2008

A microprocessor having at least one application specific functional unit and method to design same

Paolo Ienne

Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techn ...

2008

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...

2008

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