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Paolo Ienne

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Publications associées (132)

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Paolo Ienne, Andrew James Becker, Wei Hu, Ryan Charles Kastner

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...

Assoc Computing Machinery2016

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Nithin George, Mikhail Asiatici

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Guest Editorial

Paolo Ienne

2016

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Paolo Ienne, Sadegh Yazdanshenas, Hossein Asadi

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM rela ...

Institute of Electrical and Electronics Engineers2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications

Paolo Ienne, Giovanni De Micheli, Ana Petkovska, Mathias Soeken

Lexicographic Boolean satisfiability (LEXSAT) is a variation of the Boolean satisfiability problem (SAT). Given a variable order, LEXSAT finds a satisfying assignment whose integer value under the given variable order is minimum (maximum) among all satisfi ...

Assoc Computing Machinery2016

Introduction: Special Section on Architecture of Future Many Core Systems

Paolo Ienne, Hamid Sarbazi-Azad, Hossein Asadi

Elsevier2016

Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems

Paolo Ienne, Hamid Sarbazi-Azad, Hossein Asadi

Institute of Electrical and Electronics Engineers2016

Fast Hierarchical NPN Classification

Paolo Ienne, Giovanni De Micheli, Ana Petkovska, Mathias Soeken

Classifying functions according to some common properties into libraries of functions is an important step in many logic synthesis and technology mapping algorithms used in FPGA design flows. NPN classification is one of the frequently used classifications ...

IEEE2016

Automatic wire modeling to explore novel FPGA architectures

Paolo Ienne, Grace Zgheib

2016

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

Paolo Ienne, David Novo Bruna, Grace Zgheib, Manana Lortkipanidze

2016

Enriching C-based High-Level Synthesis with parallel pattern templates

Paolo Ienne, Nithin George, Lana Josipovic

2016

Instruction Set Extensions for Secure Applications

Paolo Ienne, Francesco Regazzoni

The main goal of this paper is to expose the community to past achievements and future possible uses of Instruction Set Extension (ISE) in security applications. Processor customization has proven to be an effective way for achieving high performance with ...

Ieee2016

A technology mapper for depth-constrained FPGA logic cells

Paolo Ienne, David Novo Bruna, Grace Zgheib

2015

Automatic support for multi-module parallelism from computational patterns

Paolo Ienne, Nithin George, David Novo Bruna, David Loyd Andrews

2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Paolo Ienne, Vitor Silva, Nithin George, David Novo Bruna, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2015

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Madhura Purnaprajna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

Improved carry chain mapping for the VTR flow

Paolo Ienne, Ana Petkovska, David Novo Bruna, Grace Zgheib

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

Majority-Inverter Graph for FPGA Synthesis

Paolo Ienne, Giovanni De Micheli, Ana Petkovska, David Novo Bruna, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In this paper, we present an FPGA synthesis flow based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. MIG manipulation is supported by a consistent alge ...

2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Paolo Ienne, Xavier Jimenez, David Novo Bruna

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part brings large capacity. O ...

Assoc Computing Machinery2015

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