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Paolo Ienne

Cette personne a quitté l’EPFL

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Publications associées (132)

Page 4 sur 7

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Paolo Ienne, Grace Zgheib, Stefan Nikolic

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

ASSOC COMPUTING MACHINERY2022

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

Paolo Ienne, Stefan Nikolic

Automated switch-block exploration gains in importance as technology scaling brings more emphasis on the physical constraints, making it insufficient to rely on abstract measures of routability alone. In this work, we take an approach that significantly di ...

IEEE COMPUTER SOC2021

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-or ...

Association for Computing Machinery, Inc2024

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar, Ajay Kumar Verma

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Paolo Ienne, Andreas Peter Burg, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna, Gabriel Falcao Paiva Fernandes

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime

Paolo Ienne, David Novo Bruna, Xavier Jimenez

Hybrid flash architectures combine static partitions in Sing le Level Cell (SLC) mode with partitions in Multi Level Cell (MLC) mode. Compared to MLC-only solutions, the former exploits fast and short random writes while the latter brings large capacity. O ...

Ieee2012

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Paolo Ienne

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM rela ...

Institute of Electrical and Electronics Engineers2016

Using 3D Integration Technology To Realize Multi-Context Fpgas

Yusuf Leblebici, Paolo Ienne, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar, Maurizio Skerlj

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

ShiDianNao: shifting vision processing closer to the sensor

Paolo Ienne, Robert Fasthuber

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

ACM2015

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Yusuf Leblebici, Paolo Ienne, Francesco Regazzoni

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using stati ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2011

ElasticMiter: Formally Verified Dataflow Circuit Rewrites

Paolo Ienne, Ayatallah Ahmed Gamal Kamal Elakhras

Dataflow circuits have been studied for decades as a way to implement both asynchronous and synchronous designs, and, more recently, have attracted attention as the target of high-level synthesis (HLS) compilers. Yet, little is known about mechanisms to sy ...

ACM2025

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; ho ...

2010

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Paolo Ienne, Madhura Purnaprajna

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimising this performance gap by using fixed, fine-grained, non-programmable logic structures in place o ...

Ieee2013

Fast Hierarchical NPN Classification

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Ana Petkovska

Classifying functions according to some common properties into libraries of functions is an important step in many logic synthesis and technology mapping algorithms used in FPGA design flows. NPN classification is one of the frequently used classifications ...

IEEE2016

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Enumerating simple cycles has important applications in computational biology, network science, and financial crime analysis. In this work, we focus on parallelising the state-of-the-art simple cycle enumeration algorithms by Johnson and Read-Tarjan along ...

arXiv2022

Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip

Yusuf Leblebici, Paolo Ienne

We address the quantitative comparison of two basic connection schemes for on-chip communication, connection-oriented and connection-less, regarding their enforcement of a defined Quality-of-Service for the communication. For such comparison, we have built ...

2005

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008