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Séance de cours

Tableaux de portes programmables sur le terrain (FPGA)

Dans cours

EE-334: Digital systems design

Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware. They learn how to design synchronous digital circuits on register transfer level, analyse their timing a ...

Description

Cette séance de cours couvre les principes de base et l'architecture des Field Programmable Gate Arrays (FPGA), discutant des options de mise en œuvre des circuits numériques, de l'idée de logique programmable, du principe de logique programmable, de la logique programmable complexe précoce, de la logique programmable ET-OU et des FPGA modernes. Il explique également les problèmes de logique programmable ET-OU, les opérations logiques dans les FPGA, les blocs logiques dans les FPGA modernes, la connexion des CLB avec un routage global configurable, la programmation des FPGA, les macros complexes dans les FPGA modernes, les FPGA en tant que plate-forme System on Chip (SoC) et le flux de mise en œuvre des FPGA.

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Enseignant·e

Andreas Peter Burg

Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006. In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor. In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP). Research interests and expertise

Circuits and systems for telecommunications (wireless and wired)
Prototyping and silicon implementation of new communication technologies
Development of communication algorithms and optimization for hardware implementation
Low-power VLSI signal processing for communications and other applications
Digital integrated circuits
Circuits for image and video processing

Source officielle

Proximité ontologique

Génie informatique

Matériel informatique: Application-specific integrated circuit, Microprocesseur

Concepts associés (32)

Field-programmable gate array

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together.

Circuit logique programmable

Un circuit logique programmable ou PLD (Programmable Logical Device), est un circuit intégré logique qui peut être programmé après sa fabrication. Il se compose de nombreuses cellules logiques élémentaires contenant des bascules logiques librement connectables. L'utilisateur doit donc programmer le circuit avant de l'utiliser. Les différentes logiques de programmation (unique, reprogrammable) et d'architecture ont conduit à la création de sous-familles dont les plus connues sont les FPGA et les CPLD.

Programmable Array Logic

Programmable Array Logic (PAL) is a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor. PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.

Complex programmable logic device

A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The main building block of the CPLD is a macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. Some of the CPLD features are in common with PALs: Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up.

Synthèse logique

En électronique, la synthèse logique (RTL synthesis) est la traduction d'une forme abstraite de description du comportement d'un circuit (voir Register Transfer Level) en sa réalisation concrète sous forme de portes logiques. Le point de départ peut être un langage de description de matériel comme VHDL ou Verilog, un schéma logique du circuit. D'autres sources sont venues s'additionner depuis les années 2010, comme l'utilisation de la programmation en OpenCL. Le point d'arrivée peut être un code objet pour un CPLD ou FPGA ou la création d'un ASIC.

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Séances de cours associées (30)

Circuits logiques programmables, FPGA

Explore la classification des circuits logiques, la méthodologie de conception FPGA, la mise en œuvre et l'architecture Altera Cyclone IV.

Périphériques logiques programmables : PAL, GAL, CPLD Connectez-vous à Mediaspace pour regarder cette vidéo

Couvre PAL, GAL, CPLD et la transition vers les FPGA en utilisant des HDL.

Périphériques logiques programmables : PAL, GAL, CPLD Connectez-vous à Mediaspace pour regarder cette vidéo

Couvre PAL, GAL, CPLD, et l'évolution vers les FPGA, en expliquant leur architecture et leurs avantages.

Dispositifs logiques programmables : introduction à GAL et CPLD Connectez-vous à Mediaspace pour regarder cette vidéo

Présente GAL et CPLD, couvrant l'évolution PAL, les limitations GAL et l'architecture CPLD.

Logic Design : règles de base et expansion de Shannon Connectez-vous à Mediaspace pour regarder cette vidéo

Couvre les règles de base de la conception logique et l'expansion de Shannon dans les fonctions booléennes.

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Concepts associés (32)

Field-programmable gate array

Circuit logique programmable

Programmable Array Logic

Complex programmable logic device

Synthèse logique

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