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Concept

Logic level

Publications associées (28)

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

Alexandre Schmid, Mehdi Saberi

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

IEEE2023

Towards Single Photon Detection with Amorphous Silicon Based Microchannel Plates

Janina Christine Isabelle Löffler

An exciting new approach for microchannel plate (MCP) detectors could help make them suitable for single photon detection. State-of-the-art clean room technology allows amorphous silicon based microchannel plates (AMCPs) to take a variety of shapes. This v ...

EPFL2021

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Mihai Adrian Ionescu, Igor Stolichnov, Ali Saeidi, Matteo Cavalieri, Teodor Rosca, Carlotta Gastaldi, Sadegh Kamaei Bahmaei, Eamon Patrick O'Connor

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applicati ...

AMER INST PHYSICS2021

A Deeper Look at the Energy Consumption of Lightweight Block Ciphers

Francesco Regazzoni, Subhadeep Banik, Andrea Felice Caforio, Muhammed Fatih Balli

In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. In the past there have been numerous papers that have looked at circuit level implementation of block ciphers ...

IEEE2021

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Mathias Soeken, Eleonora Testa

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

2020

Intrinsic or nucleation-driven switching: An insight from nanoscopic analysis of negative capacitance Hf1-xZrxO2-based structures

Mihai Adrian Ionescu, Igor Stolichnov, Matteo Cavalieri, Carlotta Gastaldi

HfO2-based ferroelectrics have dramatically changed the application perspectives of polarization-switching materials for information processing and storage. Their CMOS compatibility and preservation of high reversible polarization down to a few nanometer t ...

AMER INST PHYSICS2020

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

2019

SAT-Based Exact Synthesis for Multi-Level Logic Networks

Winston Jason Haaswijk

Today, the design of electronic systems is largely automated. The practice of using software automation technologies for the design of electronic hardware is commonly referred to as Electronic Design Automation (EDA). EDA comprises a large set of tools, fr ...

EPFL2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

ReRAM From Material Study to CMOS Co-integration

Elmira Shahrabi

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

EPFL2019

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Amongst 2-dimensional (2D) semiconductors of the transition-metal di-chalcogenide (TMDC) family [1], tungsten diselenide (WSe2) has shown ambipolar behavior [2], [3] coupled with high carrier mobility [4] and CMOS-like devices have been experimentally demo ...

IEEE2018

Integrated Bio/Nano/CMOS Interfaces for Electrochemical Molecular Sensing

Sandro Carrara

Integrated bio/nano/Complementary Metal-Oxide-Semiconductor (CMOS) interfaces for electrochemical molecular sensing are becoming more and more common in the literature, especially for developing new electronic biochips for smart and intelligent Internet-of ...

WILEY2018

All-optical flip-flop based on dynamic Brillouin gratings

Luc Thévenaz, Marcelo Alfonso Soto Hernandez, Andrey Denisov

One of the most essential building blocks in modem electronics is the flip-flop. A flip-flop operates bi-stably between two states, remaining at a given output level (high or low level) until a specific input control signal changes. For many years, photoni ...

IEEE2017

Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

Edoardo Charbon

In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons s ...

2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

Exploiting Circuit Duality to Speed Up SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check dete ...

IEEE2015

Polarity Control at Runtime : from Circuit Concept to Device Fabrication

Michele De Marchi

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...

EPFL2015