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Concept

Coffee Lake

Publications associées (8)

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Andreas Peter Burg, Robert Giterman, Halil Andac Yigit, Emmanuel Nieto Casarrubias

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process node ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

NrOS: Effective Replication and Sharing in an Operating System

Sanidhya Kashyap

Writing a correct operating system kernel is notoriously hard. Kernel code requires manual memory management and type-unsafe code and must efficiently handle complex, asynchronous events. In addition, increasing CPU core counts further complicate kernel de ...

USENIX ASSOC2021

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Hasene Gülperi Özsema

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

EPFL2017

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Pinar Tözün, Ippokratis Pandis, Danica Porobic, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

OLTP on Hardware Islands

Anastasia Ailamaki, Ippokratis Pandis, Danica Porobic, Pinar Tözün, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

2012

Reliability-Aware Design for Nanometer-Scale Devices

Giovanni De Micheli, David Atienza Alonso, Luca Benini, José Luis Ayala Rodrigo, Pablo Garcia del Valle

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expecte ...

2008

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

David Atienza Alonso, José Luis Ayala Rodrigo, Pablo Garcia del Valle

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be ...

IEEE Computer Society2008