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Publications associées (30)

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An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch

The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is ofte ...

Assoc Computing Machinery2017

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch

The energy e fficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is o e ...

2017

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

Christian Enz, Claudio Bruschini, Farzan Jazaeri, Chunmin Zhang, Alessandro Pezzotta

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fab ...

IEEE2016

Comment on 'Germanium electron-hole bilayer tunnel field-effect transistors with a symmetrically arranged double gale'

Mihai Adrian Ionescu, Cem Alper, José Luis Padilla de la Torre

In this comment we demonstrate that the inclusion of field--induced quantum confinement effects through appropriate discretization of conduction and valence bands refutes the suitability of a germanium electron--hole bilayer tunnel field-effect transistor ...

Institute of Physics2015

A charge carrier transport model for donor-acceptor blend layers

Wolfgang Richard Tress

Highly efficient organic solar cells typically comprise donor-acceptor blend layers facilitating effective splitting of excitons. However, the charge carrier mobility in the blends can be substantially smaller than in neat materials, hampering the device p ...

American Institute of Physics2015

Dielectric pads and low- B1+ adiabatic pulses: Complementary techniques to optimize structural T1w whole-brain MP2RAGE scans at 7 tesla

Tobias Kober, José Pedro Rebelo Ferreira Marques, Gunnar Krüger, François Lazeyras, Kieran O'Brien

Purpose To evaluate the combination of low-B1+ adiabatic pulses and high permittivity (εr ≈ 165) dielectric pads effectiveness to reproducibly improve the inversion efficiency for whole-brain MP2RAGE scans, at ultra-high field. Materials and Methods Two lo ...

Wiley-Blackwell2014

Junctionless nano-electro-mechanical resonant transistor

Mihai Adrian Ionescu, Sebastian Thimotee Bartsch

A junctionless Nano-Electro-Mechanical (NEM) resonator, comprising a highly doped conductive channel (4) connecting a drain (9) and a source (10) electrode and movably fixed by at least two ends (11, 11') acting as said source and drain electrodes, respect ...

2014

Impact of enhanced contact doping on minority carriers diffusion currents

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

Minority carriers diffusion currents are particularly important in parasitic substrate couplings of Smart Power ICs. In CMOS technologies the P-substrate potential is imposed by P+ contacts and N-wells by N+ highly doped implantations. The doping concentra ...

IEEE2014

A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

In this paper, we demonstrate a steep Subthreshold Slope (SS) silicon FinFET with Schottky-barrier source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA ...

2014

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

Yusuf Leblebici, Bahman Kheradmand Boroujeni, Christian Piguet

A new circuit style is proposed to tune the delay, subthreshold leakage (ISUB), and gate leakage (IG) of high fan-in multiplexer circuits, such as the FPGA Look-Up Table (LUT) and Switch-Box (SB), without increasing the Gate Induced Drain Leakage (GIDL) cu ...

American Scientific Publishers2013