Giovanni De MicheliExpertise
Technologies de conception pour les systèmes intégrés, tels que la synthèse, le codesign de HW/SW et la conception de basse puissance. Technologies de conception des systèmes sur les plateformes hétérogènes comprenant les composants électriques, et biologiques.
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Enseignement et PhD A dirigé les thèses EPFL de Abhishek Garg, Mohamed Haykel Ben Jamaa, Francesco Zanini, Ciprian Seiculescu, Cristina Boero, Hu Xu, Andrea Cavallini, Shashi Kanth Herbert SheaEnseignement et PhD Doctorant·es actuel·les Myoung Ju Kim, Xintong Tong, Huapeng Zhang, Rohit Kadungamparambil John, Yichi Luo, Lucas Aurélien Jourdan, Ayana Mizutani, Donghyun Kim A dirigé les thèses EPFL de Michael Bodendorfer, Renato Krpoun, Samuel Rosset, Muhamed Niklaus, Kaustav Ghose, Samin Akbari, Vinu Lalgudi Venkatraman, Luc Maffli, Simon Dandavino, Tobias Bandi, Subha Chakraborty, Pietro Romano, Alexandre Poulin, Marianna Fighera, Nadine Besse, Alexis Pierre Henri Marette, Reto Wiesendanger, Fr
David Atienza AlonsoDavid Atienza Alonso is an associate professor of EE and director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) servers and edge AI architectures. Dr. Atienza has co-authored more than 350 papers, one book, and 12 patents in these previous areas. He has also received several recognitions and award, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned two best paper awards at the VLSI-SoC 2009 and CST-HPCS 2012 conference, and five best paper award nominations at the DAC 2013, DATE 2013, WEHA-HPCS 2010, ICCAD 2006, and DAC 2004 conferences. He serves or has served as associate editor of IEEE Trans. on Computers (TC), IEEE Design & Test of Computers (D&T), IEEE Trans. on CAD (T-CAD), IEEE Transactions on Sustainable Computing (T-SUSC), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019 and was GOLD member of the Board of Governors of IEEE CASS from 2010 to 2012. He is a Distinguished Member of ACM and an IEEE Fellow.
Pierre-André FarinePierre-André Farine received the Doctoral and Engineering Degrees in Microtechnology from University of Neuchâtel, Switzerland, respectively in 1984 and 1978, and the Engineering in Microtechnology from ETS Le Locle in 1974.
He was working 17 years for the Swiss watch industries (Swatch Group), including developments for high-tech products, such as pager watches, watches including integrated sensors such as pressure, compass, altimeter and temperature sensors for Tissot. He was also involved in prototypes developments for watches including GPS and cellular GSM phones.
Since 8 years, he is Professor in Electronics and Signal Processing at the Institute of Microtechnology IMT, University of Neuchâtel, Switzerland. Full professor at EPFL since January 1st, 2009, he works in the field of low-power integrated products for portable devices, including microelectronics for wireless telecommunications, UWB and GNSS systems. He is Head of the Electronics and Signal Processing Laboratory ESPLAB of the EPFL IMT-NE. His laboratory works also for video and audio compression algorithms and their implementation in low power integrated circuits.
Jürgen BruggerI am a Professor of Microengineering and co-affiliated to Materials Science. Before joining EPFL I was at the MESA Research Institute of Nanotechnology at the University of Twente in the Netherlands, at the IBM Zurich Research Laboratory, and at the Hitachi Central Research Laboratory, in Tokyo, Japan. I received a Master in Physical-Electronics and a PhD degree from Neuchâtel University, Switzerland. Research in my laboratory focuses on various aspects of MEMS and Nanotechnology. My group contributes to the field at the fundamental level as well as in technological development, as demonstrated by the start-ups that spun off from the lab. In our research, key competences are in micro/nanofabrication, additive micro-manufacturing, new materials for MEMS, increasingly for wearable and biomedical applications. Together with my students and colleagues we published over 200 peer-refereed papers and I had the pleasure to supervise over 25 PhD students. Former students and postdocs have been successful in receiving awards and starting their own scientific careers. I am honoured for the appointment in 2016 as Fellow of the IEEE “For contributions to micro and nano manufacturing technology”. In 2017 my lab was awarded an ERC AdvG in the field of advanced micro-manufacturing.
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Tobias KippenbergEnseignement et PhD Doctorant·es actuel·les Mengxin Lin, Xinru Ji, Shuhang Zheng, Junyin Zhang, Zhuoya Yuan, Evgenii Guzovskii, Mahdi Chegnizadeh, Jiale Sun, Shivaprasad Umesh Hulyal, Xiaoyi Cheng, Hao Li, Nikolai Kuznetsov, Alessio Zicoschi, Jiahe Pan, Mikael Sebastian Reichler, Xuxin Wang, Donato Manuel Jiménez Benetó, Xuan Yang, Hugo Paul Arbez, Amirali Arabmoheghi, Viacheslav Snigirev, Alisa Davydova, Zihan Li, Giovanni Scarioni A dirigé les thèses EPFL de Stefan Weis, Emanuel Gavartin, Xiaoqing Zhou,
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