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Concept

Chronologie des microprocesseurs

Publications associées (27)

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Giovanni De Micheli, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Michele De Marchi, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Giovanni De Micheli, Yusuf Leblebici, Andreas Peter Burg, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Institute of Electrical and Electronics Engineers2014

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...

2013

Opportunities for high-pressure microfluidics in biomedical applications

Ata Tuna Ciftlik

Pressure lies at the basis of operation of most microfluidic systems, and is a determinant factor in the extent of miniaturization and in limiting the throughput and time constant of the microfluidic assays. Despite the apparent importance given to fluidic ...

EPFL2013

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Mihai Adrian Ionescu, Arnab Biswas, Wladyslaw Grabinski, Surya Shankar Dan

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

Elsevier2012

A low power, low chip area decimation filter for Σ - Δ modulator for flywheel MEMS gyro realized in the CMOS 180 nm technology

Pierre-André Farine, Rafal Tomasz Dlugosz, Steve Tanner, Patrick Stadelmann

The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in ...

IEEE2012

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012