Double multiplication region configuration for near-infrared sensitivity enhancement in silicon cmos single-photon avalanche diodes

A near-infrared sensitivity enhanced substrate non-isolated silicon single-photon avalanche diode is disclosed, comprising a p-well layer (101), a high-voltage n-well (102), the p-well layer and the high- voltage n-well layer positioned against each other and configured to form a main junction (100) defining an active area (104), the p- well layer comprising a doping according to a doping concentration distribution, the p-well layer being configured to have first double peaks in its doping concentration distribution throughout the p-well layer in the active area, corresponding to respective p-doped regions, and the high-voltage n-well being configured to have second double peaks, corresponding to respective n-doped regions configured to achieve a n-p-n-p type device junction profile, whereby further the p- well layer is lightly doped and configured to obtain a wide depletion region, i.e., at least 1 μm wide, the high-voltage n-well layer being further configured to extend beyond the p-well layer to form a guard ring (103) around the active area.