Speed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs

Giulia Beanato
2014
Theses

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Giulia Beanato
2014
Theses

Official source

Related publications (3)

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Related publications (3)

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Babak Falsafi, Dorde Jevdic, Ilknur Cansu Kaynak

Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of o ...

IEEE2014

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Alessandro Cevrero, Michail Zervas, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation

David Atienza Alonso, José Luis Ayala Rodrigo, Pablo Garcia del Valle

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be ...

IEEE Computer Society2008