Bringing NoCs to 65nm

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consum ...

Biologically inspired solid-state nanopores are artificial openings or apertures in thin membranes similar to natural protein ion channels in a lipid bilayer of cell membranes. In solid-state nanopores, a thin insulating membrane with single or multiple po ...

The fabrication of metallic nanostructures on stretchable substrates enables specific applications that exploit the combination of the nano-scale phenomena and the mechanical tunability of the physical dimensions of the nanostructures. Due to the large dif ...

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

In this work, we demonstrate a new thermal management approach for direct cooling of GaN-on-Si power integrated circuits (ICs), in which the Si substrate functions as a microfluidic heat sink, turning Si into a cost-effective, high thermal performance subs ...

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

Integration of CMOS electronic circuits and electromechanical resonators has been pursued for a long time by many different research groups and even foundries. This would improve the overall performance of electromechanical oscillators and sensors. However ...

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

The evolution and characteristics of the electronics is directly linked to the technological and societal progress. Today, there is a huge variety of electronic solutions offered, with the RF low-power systems, such as wireless sensor networks, wireless bo ...

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

This paper proposes an unconventional image acquisition scheme for machine vision applications, based on detecting ratios of illumination (pixel) intensities. Detecting relative ratios enables capturing the scene features and patterns almost independently ...

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the req ...

A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the ...

Since the first introduction of digital cameras, the camera market has been taking tremendous interest from many fields. This trend has even accelerated when the cost, size, and power consumption of such devices were reduced with the introduction of camera ...

The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high F t can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GH ...

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this ...

Bringing NoCs to 65nm

Chat with Graph Search

Computational Imaging SPAD Cameras

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

2D MoS2 Nanopores: Wafer-scale Fabrication and Monolayer Stability for Long-term Single-Molecule Sensing

Scalable fabrication of functional nanostructures on stretchable substrates by capillary-assisted particle assembly and adhesion lithography

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

Embedded Microchannel Cooling for High Power-Density GaN-on-Si Power Integrated Circuits

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

ReRAM From Material Study to CMOS Co-integration

Three-Dimensional Nano-Acoustic Bragg Reflectors for CMOS Embedded NEMS

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Characterization and modeling of nanoscale MOSFET for ultra-low power RF IC design

Sub-electron CIS noise analysis in 65 nm process

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

A Low Power On-Chip Class-E Power Amplifier For Remotely Powered Implantable Sensor Systems

A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation

Design and Implementation of CMOS Image Sensors for Biomedical Applications

Low-power RF modeling of a 40nm CMOS technology using BSIM6

Effects of Process Variations on 3-D Global Clock Distribution Networks