An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consuming a total of 205 mu W DC power from 0.48 V and 1 V supplies. Of the total power consumption, 56% (115 mu W) is consumed by the digital logic, 16% (33 mu W) by the on-chip clock oscillator, and 28% (57 mu W) by the RF switch used as a backscatter modulator. The ASIC broadcasts up to 1000 BLE advertising packets per second at a data rate of 1 Mbps, yielding a backscatter modulator efficiency of 57 pJ/bit. The device was validated in both cabled and wireless (over-the-air) measurement setups, demonstrating compatibility with unmodified smartphones as well as commercially available BLE chips, such as the Nordic Semiconductor nRF51822. With the wireless test setup used in this work, and assuming a +10 dBm carrier source, the ASIC has a theoretical maximum read range of 4.9 m using a smartphone as the receiver. Building from previous work in BLE backscatter communication using FPGA-based prototypes, this work provides an important quantitative demonstration of the size and power savings that can be achieved in a BLE-compatible backscatter ASIC.