Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, time and cost effective integration technique and at the same time provide device stability with CMOS-compatible materials that are used in the relevant device applications. In this study, we demonstrate a technique for the nm-scale hybrid integration of ReRAM on the foundry-produced CMOS 180 nm technology chip. Tungsten (W), as a material of choice for vertical vias in CMOS circuitry, is employed as the ReRAM electrode. However, W oxidizes readily, having multiple oxidation states, which influences the device reliability. In particular, the generation of semi-stable oxides at the electrode/switching layer (W/HfO2) interface has a profound influence on device performance. To achieve reliable W-based integrated ReRAM, we modulated and controlled the W electrode oxidation within the different co-integrated ReRAM stacks by increasing HfO2 switching layer thickness, through the post-metallization annealing under O-2-ambient, and by adding an Al2O3 barrier layer between the W and HfO2 layers. The effect of W interface modifications is further studied through the analysis of switching mechanism and TEM micro-structural characterization. A notable improvement in HRS/LRS resistance ratio and switching stability was observed in optimally fabricated (W/Al2O3/HfO2/TiN) ReRAM on the back end of the line (BEoL) of 180 nm CMOS chip.