Publications related to Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Related publications (32)

Measuring electrical properties in semiconductor devices by pixelated STEM and off-axis electron holography (or convergent beams vs. plane waves)

We demonstrate the use of both pixelated differential phase contrast (DPC) scanning transmission electron microscopy (STEM) and off-axis electron holography (EH) for the measurement of electric fields and assess the advantages and limitations of each techn ...

Pergamon-Elsevier Science Ltd2024

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Carlotta Gastaldi

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they ...

EPFL2022

Adaptive Body Biasing in Strong Body Factor Technologies

Thomas Christoph Müller

With the advent of intelligent sensor nodes in everyday life, low power aspects of system design become more and more important. Adaptive body biasing is a promising methodology to achieve dynamic adaptation of the tradeoff between performance and energy b ...

EPFL2021

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Mohammad Samizadeh Nikooytabalvandani, Catherine Erine, Minghua Zhu, Pirouz Sohi

In this letter, we present a new concept for normally-off AlGaN/GaN-on-Si MOS-HEMTs based on the combination of p-GaN, tri-gate and MOS structures to achieve high threshold voltage (V-TH) and low on-resistance (R-ON). The p-GaN is used to engineer the band ...

Institute of Electrical and Electronics Engineers2021

Enhancement Mode Tri-gate GaN Power Devices and Logic Circuits

Minghua Zhu

Gallium Nitride (GaN) is one of the most promising materials for high frequency power switching due to its exceptional properties such as large saturation velocity, high carrier mobility, and high breakdown field strength. The high switching frequency of G ...

EPFL2021

Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

Chunmin Zhang

Total ionizing radiation compromises electrical characteristics of microelectronic devices and even causes functional failures of integrated circuits. It has been identified as a potential threat to electronic components, especially those in high-energy ph ...

EPFL2021

In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation

Edoardo Charbon, Christian Enz, Farzan Jazaeri, Hung-Chi Han, Antonio D'Amico

In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-of ...

IEEE2021

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M Beckers

Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative mi ...

EPFL2021

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Mihai Adrian Ionescu, Igor Stolichnov, Ali Saeidi, Matteo Cavalieri, Teodor Rosca

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

AMER CHEMICAL SOC2020

Quantum Transport in 40-nm MOSFETs a Deep-Cryogenic Temperatures

Edoardo Charbon, Andrea Ruffino, Yatao Peng

In this letter, we characterize the electrical properties of commercial bulk 40-nm MOSFETs at room and deep cryogenic temperatures, with a focus on quantum information processing (QIP) applications. At 50 mK, the devices operate as classical FETs or quantu ...

Institute of Electrical and Electronics Engineers2020

Deep-UV-Enhanced Approach for Low-Temperature Solution Processing of IZO Transistors with High-k AlOx/YAlOx Dielectric

Danick Briand, Jaemin Kim, Alessio Mancinelli

Solution processing is an attractive alternative to standard vacuum fabrication techniques for the large-area manufacturing of metal oxide (MOx)-based electron devices. Here, we report on thin-film transistors (TFTs) based on a solution-processed indium zi ...

AMER CHEMICAL SOC2020

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Mihai Adrian Ionescu, Matteo Cavalieri, Nicolò Oliva, Luca Capua

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Seve ...

NATURE PUBLISHING GROUP2020

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabr ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Subthermionic negative capacitance ion sensitive field-effect transistor

Mihai Adrian Ionescu, Ali Saeidi, Francesco Bellando, Carlotta Gastaldi

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for th ...

2020

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Christian Enz, Arnout Lodewijk M Beckers, Farzan Jazaeri

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, ...

2020

Diffraction artefacts from twins and stacking faults, and the mirage of hexagonal, polytypes or other superstructures

Cyril Cayron

Recently, a hexagonal phase has been reported in high carbon steels in several studies. Here, we show that the electron microscopy results used in these studies were erroneously interpreted. The extra-spots in the diffraction patterns and the odd contrasts ...

2020

Characterization and Modeling of Mismatch in Cryo-CMOS

Edoardo Charbon

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4 ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Christian Enz, Arnout Lodewijk M Beckers, Farzan Jazaeri

This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of tempe ...

Institute of Electrical and Electronics Engineers2020

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is ...

IEEE2019