A Design-oriented Charge-based Simplified Model for FDSOI MOSFETs

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Related publications (30)

Nanoscale imaging of mobile carriers and trapped charges in delta doped silicon p-n junctions

Broadband electrostatic force microscopy can be used to non-destructively image n-type and p-type dopant layers in silicon devices with a lateral resolution of 10 nm and a vertical resolution of 0.5 nm. ...

NATURE PUBLISHING GROUP2020

Quantum Transport in 40-nm MOSFETs a Deep-Cryogenic Temperatures

Edoardo Charbon, Andrea Ruffino, Yatao Peng

In this letter, we characterize the electrical properties of commercial bulk 40-nm MOSFETs at room and deep cryogenic temperatures, with a focus on quantum information processing (QIP) applications. At 50 mK, the devices operate as classical FETs or quantu ...

Institute of Electrical and Electronics Engineers2020

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Igor Stolichnov, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Neg ...

Nature Research2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

1200 V Multi-Channel Power Devices with 2.8 Ω•mm ON-Resistance

Kai Cheng, Elison de Nazareth Matioli, Jun Ma, Minghua Zhu, Catherine Erine, Luca Nela

Here we report novel multi-channel AlGaN/GaN MOSHEMTs with high breakdown voltage (V BR ) and low ON-resistance (R ON ). The multi-channel structure was judiciously designed to yield a small sheet resistance (R s ) of 80 Ω/sq using only four 2DEG channels, ...

IEEE2019

Co-integrated Subthermionic 2D/2D WSe2/SnSe2 Vertical Tunnel FET and WSe2 MOSFET on same flake: towards a 2D/2D vdW Dual-Transport Steep Slope FET

Mihai Adrian Ionescu, Nicolò Oliva, Matteo Cavalieri, Luca Capua

In this work we report the fabrication, co-integration and resulting performance of 2D/2D van der Waals (vdW) Vertical p-type Tunnel FETs and p-MOSFETs in a WSe2/SnSe2 material system. We demonstrate the best ever reported combined performance in terms of ...

IEEE2019

First Near-Ultraviolet- and Blue-Enhanced Backside-Illuminated Single-Photon Avalanche Diode Based on Standard SOI CMOS Technology

Claudio Bruschini, Edoardo Charbon, Myung Jae Lee

We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backs ...

2019

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon, Fabio Sebastiano

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is ...

IEEE2019

On the Dynamic Performance of Laterally Gated Transistors

Elison de Nazareth Matioli, Giovanni Santoruvo, Armin Jafari, Catherine Erine, Mohammad Samizadeh Nikooytabalvandani

Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...

Institute of Electrical and Electronics Engineers2019

Near Hysteresis-Free Negative Capacitance InGaAs Tunnel FETs with Enhanced Digital and Analog Figures of Merit below VDD=400mV

Igor Stolichnov, Mihai Adrian Ionescu, Ali Saeidi, Hiroshi Iwai

We report the universal boosting impact of a true negative capacitance (NC) effect on digital and analog performances of Tunnel FETs (TFETs), mirrored for the first time in near hysteresis-free experiments and exploiting the S-shaped polarization character ...

2019

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