Publications related to An Ultra-Miniaturised CMOS Clock and Data Recovery System for Wireless ASK Transmission

Related publications (13)

Ultra small biomorphic cantilevers for high-speed atomic force microscopy

Atomic force microscopy (AFM) has long been recognized as a potent tool for capturing high-resolution topographical data across a wide spectrum of samples. However, this superior spatial imaging capability has traditionally been counterbalanced by its rela ...

EPFL2025

Federated Learning Over Wireless Networks: Convergence Analysis and Resource Allocation

Vincent Gramoli

There is an increasing interest in a fast-growing machine learning technique called Federated Learning (FL), in which the model training is distributed over mobile user equipment (UEs), exploiting UEs' local computation and training data. Despite its advan ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Robust Phase Unwrapping via Deep Image Prior for Quantitative Phase Imaging

Michaël Unser, Matthias Lütolf, Nathalie Brandenberg, Thanh-An Michel Pham

Quantitative phase imaging (QPI) is an emerging label-free technique that produces images containing morphological and dynamical information without contrast agents. Unfortunately, the phase is wrapped in most imaging system. Phase unwrapping is the comput ...

2021

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Physical Layer Aspects of LoRa and Full-Duplex Wireless Transceivers

Orion Afisiadis

Wireless communications are currently faced with two main challenges. The first challenge stems from the enormous number of Internet of Things (IoT) devices that transmit very small amounts of data. The second challenge is the need for ever-increasing data ...

EPFL2020

On the Universality of Low-Density Parity-Check Block Codes

Rüdiger Urbanke, Wei Liu

An important class of modern channel codes is the capacity-achieving sequences of low-density parity-check block codes. Such sequences are usually designed for the binary erasure channel and are decoded by iterative message-passing algorithms. In this pape ...

IEEE2020

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Philip Brisk, Mirjana Stojilovic

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Alessandro Cevrero, Thomas Toifl, Lukas Kull, Ilter Ozkaya, Gain Kim, Cosimo Aprile

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

2018

A 51.4 Mb/s FSK Transmitter Employing a Phase Domain Digital Synthesizer with 1.5 mu s Start-up for Energy Efficient Duty Cycling

Christian Enz, Nicola Scolari, David Ruffieux, Raghavasimhan Thirunarayanan

This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a star ...

Ieee2016

CMOS-Integrated Photodetectors for Neuromorphic and Smart Imaging Applications: a Low-Cost Design and Measurement Method

Yusuf Leblebici, Alexandre Schmid, Nikola Katic

2014

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...

EPFL2006

First Fully CMOS-Integrated 3D Hall Probe

Radivoje Popovic, Pavel Kejik, Enrico Schurig

We present the first fully CMOS-integrated 3D Hall probe. The microsystem is developed for precise magnetic field measurements in the range from mT up to tens of tesla in the frequency range from DC to 30 kHz and with a spatial resolution of about 150 μm. ...

2005