Mohamed Haykel Ben Jamaa

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During many decades, Moore's law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry pre ...

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their org ...

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

In this paper, we demonstrate the ability of the multi- spacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize sin ...

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correc ...

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properti ...

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using mu ...

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of buildin ...

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform u ...

Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this paper, we propose for the first time the utilization of the multi-spacer patt ...

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer ...

Mohamed Haykel Ben Jamaa

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Fabrication and design of nanoscale regular circuits

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Prospects for logic-on-a-wire

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Programmable Logic Circuits based on Ambipolar CNFET

Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique

Improving the Fault Tolerance of Nanometric PLA Designs

Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays