Publications by Seyed Armin Tajalli

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The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing ...

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based ...

A time-division multiplexing (TDM) digital channel coding scheme with inter-symbol interference (ICI) reduction property for multi-drop memory interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TD ...

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to ...

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted si ...

A current-mode

\Delta\Sigma

analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power p ...

This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

A sixth-order low-pass

g_m

-C filter with a very wide tuning range (

f_c

= 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single stage folded-cascode transcon ...

This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption ...

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is c ...

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement ...

A compact high-value ﬂoating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 um CMOS technology to verify the proposed concept. This technique has been applied to design a reconﬁgurable sixt ...

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

A transceiver (TRX) architecture employing spectrum shaping signaling scheme is proposed, which can significantly reduce inter-symbol interference (ISI) and crosstalk in multi-drop interfaces. The proposed TRX architecture relies on digital implementation ...

Seyed Armin Tajalli

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Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Implementing Ultra-high-Value Floating Tunable CMOS Resistors

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces