Publications by Wladyslaw Grabinski

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In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5 ...

In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOSFETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as h

There are several techniques for junction profiling available in literature, yet none of them are practically suitable for the accurate determination of the lateral junction steepness in TFET devices, which is the most important parameter influencing TFET ...

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated.

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 μm long suspended Si nanowire MOSFETs, the highest process-based stress record in MOSFETs until now, by elastic local buckling. Significant stress level modulation in the channel from 1.2 to 5.6 GPa on a single wafer is demonstrated for the first time by varying the NW width. The GAA Si NW MOSFET with 5.6 GPa uniaxial tensile stress is characterized a

This paper reports a simulation based study of the non-local tunneling model using a commercially available technology computer-aided design (TCAD) device simulator. Single gate Tunnel FET devices with 400nm gate length based on SOI technology are measured ...

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices ...

Wladyslaw Grabinski

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Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Accumulation-Mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain

A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

TCAD Simulation of SOI TFETs and Calibration of Non-local Band-to-Band Tunneling Model

Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

Gate-All-Around Buckled Dual Si Nanowire nMOSFETs on Bulk Si for Transport Enhancement and Digital Logic Application