Publications by Yusuf Leblebici

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Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

In this paper, the impact of the wire grid size on the power-delay-area trade off of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complet ...

The fourth edition of CMOS Digital Integrated Circuits: Analysis and Design continues the well-established tradition of the earlier editions by offering the most comprehensive coverage of digital CMOS circuit design, as well as addressing state-of-the-art technology issues highlighted by the widespread use of nanometer-scale CMOS technologies. In this latest edition, virtually all chapters have been re-written, the transistor model equations and device parameters have been revised to reflect the sigificant

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing t ...

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

A compact high-value ﬂoating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 um CMOS technology to verify the proposed concept. This technique has been applied to design a reconﬁgurable sixt ...

Creating panoramic images has become a popular feature in modern smart phones, tablets, and digital cameras. A user can create a 360 degree field-of-view photograph from only several images. Quality of the resulting image is related to the number of source ...

Coupling coefficients calculation is known to be a critical issue in embedded Non-Volatile Memory (eNVM) compact modeling. In this paper we have implemented the charge balance method within the Brew’s Charge Sheet Model equation, determining the floating g ...

This paper presents a new VHDL-AMS behavioral model of an electrochemical cell suitable for the design of VLSI bio-chips. Existing models are mainly equivalent circuit macromodels using electrical primitives, which hardly fit the actual behavior of biosens ...

Real-time disparity estimation requires real-time rectification which involves solving the models of lens distortions, image translations and rotations. Low complexity look-up-table based rectification algorithms usually require an external memory to store ...

Wireless implantable devices capable of monitoring the electrical activity of the brain are becoming an important tool for understanding and potentially treating mental diseases such as epilepsy and depression. While such devices exist, it is still necessary to address several challenges to make them more practical in terms of area and power dissipation.In this work, we apply Learning Based Compressive Subsampling (LBCS) to tackle the power and area trade-offs in neural wireless devices. To this end, we pro

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing ...

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for a-priori functional fault tolerance analysis was developed. It is a statistical Monte Carlo based tool that induces different failure models, and does subsequent evaluation of system reliability under realistic constraints. A structured fault modeling arch

Neuromorphic systems using memristive devices provide a brain-inspired alternative to the classical von Neumann processor architecture. In this work, a spiking neural network (SNN) implemented using phase-change synapses is studied. The network is equipped ...

Panoptic is a custom spherical light field camera used as a polydioptric system where imagers are distributed over a spherical geometry, each having its own vision of the surrounding and a distinct focal plane. The spherical light field camera records ligh ...

A power and area efficient hardware encoding system tailored for wireless implantable applications is presented. Constant medical monitoring allowed by implantable devices is the most relevant alternative to current bulky monitoring systems, which, in case ...

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

A transceiver (TRX) architecture employing spectrum shaping signaling scheme is proposed, which can significantly reduce inter-symbol interference (ISI) and crosstalk in multi-drop interfaces. The proposed TRX architecture relies on digital implementation ...

Yusuf Leblebici

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Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff

CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition

Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime

System Level simulation framework for the ASICs development of a novel particle physics detector

Implementing Ultra-high-Value Floating Tunable CMOS Resistors

FIR filters for hardware-based real-time multi-band image blending

Embedded non–volatile memory study with surface potential based model

VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

A Methodology for Reliability Enhancement of Nanometer- Scale Digital Systems Based on A-Priori Functional Fault- Tolerance Analysis

Unsupervised Learning Using Phase-Change Synapses and Complementary Patterns

Real-time Implementation of Gaussian Image Blending in a Spherical Light Field Camera

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces