Skip to main content
Graph
Search
fr
en
Login
Search
All
Categories
Concepts
Courses
Lectures
MOOCs
People
Quizes
Exercises
Publications
Startups
Units
Show all results for
Home
Lecture
Hardware Description Languages
Graph Chatbot
Related lectures (33)
High-Level Synthesis: Formally Verified Elastic Circuits
Presents the development of a verified high-level synthesis compiler for elastic circuits.
Parallel Port & Nios II Interrupts
Covers the design of a programmable parallel port interface for an Avalon bus and the architecture of the Nios II processor.
Automatic Optimization of Arithmetic Circuits
Explores automatic optimization of arithmetic circuits, addressing challenges in restructuring circuits for improved efficiency and performance.
Programmable Logic Circuits, FPGA
Explores logic circuit classification, FPGA design methodology, implementation, and Altera Cyclone IV architecture.
Introduction au VHDL
Covers VHDL basic concepts, program structure, objects, types, operators, literals, and arrays.
Semicustom RTL Design: Frontend with Synthesis
Log in to Mediaspace to watch this video
Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.
FPGA Programming with Speedgoat: A Comprehensive Overview
Log in to Mediaspace to watch this video
Covers FPGA programming with Speedgoat, focusing on synthesis, design practices, and practical examples.
VHDL for Simulation & Testbenches
Log in to Mediaspace to watch this video
Explores VHDL for simulation, debugging, time modeling, event-based simulation, and testbench creation in digital system design.
Semicustom RTL Design: Design Flow and Standard Cells
Log in to Mediaspace to watch this video
Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.
Field Programmable Gate Arrays (FPGAs)
Log in to Mediaspace to watch this video
Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.
FPGA Programming with Speedgoat: Real-Time Signal Processing
Log in to Mediaspace to watch this video
Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.
Simulation-Based Verification
Log in to Mediaspace to watch this video
Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.
Generating a CLK Generator (PLL) IP in Vivado
Log in to Mediaspace to watch this video
Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.
Digital Logic Circuits: CMOS and Verilog Modeling
Log in to Mediaspace to watch this video
Discusses digital logic circuits, focusing on CMOS technology and Verilog modeling techniques.
VHDL for Synthesis
Log in to Mediaspace to watch this video
Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.
Digital Logic Circuits: CMOS and Verilog Design
Log in to Mediaspace to watch this video
Discusses digital logic circuits, CMOS technology, and Verilog for circuit design.
How we design chips: The Digital VLSI Design Flow
Log in to Mediaspace to watch this video
Explores the principles and methodologies for designing integrated circuits, covering design flows, VLSI styles, abstraction levels, and the semiconductor ecosystem.
Semicustom RTL Design: Backend
Log in to Mediaspace to watch this video
Explores the backend design flow in semicustom ASIC design, covering layout, clock tree generation, and tapeout preparation.
Synchronous Digital Circuits: Principles and Design
Log in to Mediaspace to watch this video
Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.
Test Environment Setup
Log in to Mediaspace to watch this video
Covers the setup of a test environment for VLSI design.
Previous
Page 1 of 2
Next
