Skip to main content
Graph
Search
fr
en
Login
Search
All
Categories
Concepts
Courses
Lectures
MOOCs
People
Quizes
Exercises
Publications
Startups
Units
Show all results for
Home
Lecture
High-Level Synthesis: Formally Verified Elastic Circuits
Graph Chatbot
Related lectures (46)
Programmable Logic Devices: PAL, GAL, CPLD
Log in to Mediaspace to watch this video
Covers PAL, GAL, CPLD, and the transition to FPGAs using HDLs.
VHDL for Synthesis
Log in to Mediaspace to watch this video
Covers basic VHDL constructs for RTL design, including arithmetic, multiplexers, registers, and instantiation.
Challenges in High-Level Synthesis: Optimizing Loop Constructs
Log in to Mediaspace to watch this video
Addresses the challenges of high-level synthesis and optimizing loop constructs using the polyhedral model for improved performance and scheduling.
Digital Design: Lowerbounds and Recommendations
Log in to Mediaspace to watch this video
Covers abstraction levels, EPFL design flow, lowerbounds, and layout recommendations.
Quantum and Nanocomputing
Log in to Mediaspace to watch this video
Covers quantum and nanocomputing, focusing on molecules as conductive elements, molecular transistors, and field coupling elements.
In-System Debug and Custom AXI IP
Log in to Mediaspace to watch this video
Covers in-system debug, marking nets, generating debug IP, and reading from a custom AXI IP.
Project: Video Game
Log in to Mediaspace to watch this video
Covers the organization, objectives, project ideas, graphics enhancement, advanced adapters, and alternative interfaces for a video game project.
Arbiter FSM & FPGA Implementation
Log in to Mediaspace to watch this video
Covers the design of an Arbiter FSM in VHDL for digital system design, emphasizing access timing management.
Semicustom RTL Design: Frontend with Synthesis
Log in to Mediaspace to watch this video
Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.
Finite State Machines (FSMs)
Log in to Mediaspace to watch this video
Explores Finite State Machines (FSMs) in digital system design, covering Mealy and Moore FSMs, state diagrams, VHDL implementation, and state encoding.
Generating a CLK Generator (PLL) IP in Vivado
Log in to Mediaspace to watch this video
Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.
Digital Logic Circuits: CMOS and Verilog Modeling
Log in to Mediaspace to watch this video
Discusses digital logic circuits, focusing on CMOS technology and Verilog modeling techniques.
Untitled
Log in to Mediaspace to watch this video
Quantum and nanocomputing
Log in to Mediaspace to watch this video
Explores digital design principles, ADC architectures, FPGA-based ADCs, figures of merit, and lower bounds in digital design.
Timing Analysis: Synchronous Circuit Design
Log in to Mediaspace to watch this video
Covers timing analysis of synchronous circuits, focusing on flip-flops, timing constraints, and metastability issues.
Feedback and Stability
Log in to Mediaspace to watch this video
Explores negative feedback in analog circuits, focusing on desensitizing gain, reducing distortion, controlling noise, and extending bandwidth.
Designing 3-Dimensional NAND Circuits: Key Considerations
Log in to Mediaspace to watch this video
Covers the design considerations for 3-dimensional NAND circuits, focusing on transistor sizing and performance optimization.
Fundamentals of Digital Systems: Sequential Logic and Memory Elements
Log in to Mediaspace to watch this video
Introduces the fundamentals of digital systems, focusing on sequential logic and memory elements like latches and flip-flops.
VHDL for Simulation & Testbenches
Log in to Mediaspace to watch this video
Explores VHDL for simulation, debugging, time modeling, event-based simulation, and testbench creation in digital system design.
Comparator Circuits
Log in to Mediaspace to watch this video
Explores comparator circuits, hysteresis, oscillators, and Wien Bridge circuits.
Previous
Page 2 of 3
Next